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Commit bfdf227d authored by David Dai's avatar David Dai Committed by Gerrit - the friendly Code Review server
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dt-bindings: cpufreq: add core count to freq-domain 



Add an additional cell to represent the number of expected
core count for the cpu, the core count is used to determine
whether or not a particular performance level is a boost
frequency.

Change-Id: I9745e5d59221def9b9f291acd14a341a20978352
Signed-off-by: default avatarDavid Dai <daidavid1@codeaurora.org>
parent b75185bd

Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt

+11 −10
Original line number Diff line number Diff line
@@ -33,7 +33,8 @@ Properties: 


* Property qcom,freq-domain

Devices supporting freq-domain must set their "qcom,freq-domain" property with

phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.

phandle to a cpufreq_hw followed by the Domain ID(0/1) and core count in the

CPU DT node.





Example:
@@ -52,7 +53,7 @@ DCVS state together. 
			reg = <0x0 0x0>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			L2_0: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;
@@ -68,7 +69,7 @@ DCVS state together. 
			reg = <0x0 0x100>;

			enable-method = "psci";

			next-level-cache = <&L2_100>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			L2_100: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;
@@ -81,7 +82,7 @@ DCVS state together. 
			reg = <0x0 0x200>;

			enable-method = "psci";

			next-level-cache = <&L2_200>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			L2_200: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;
@@ -94,7 +95,7 @@ DCVS state together. 
			reg = <0x0 0x300>;

			enable-method = "psci";

			next-level-cache = <&L2_300>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			L2_300: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;
@@ -107,7 +108,7 @@ DCVS state together. 
			reg = <0x0 0x400>;

			enable-method = "psci";

			next-level-cache = <&L2_400>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			L2_400: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;
@@ -120,7 +121,7 @@ DCVS state together. 
			reg = <0x0 0x500>;

			enable-method = "psci";

			next-level-cache = <&L2_500>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			L2_500: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;
@@ -133,7 +134,7 @@ DCVS state together. 
			reg = <0x0 0x600>;

			enable-method = "psci";

			next-level-cache = <&L2_600>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			L2_600: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;
@@ -146,7 +147,7 @@ DCVS state together. 
			reg = <0x0 0x700>;

			enable-method = "psci";

			next-level-cache = <&L2_700>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			L2_700: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;
@@ -163,7 +164,7 @@ DCVS state together. 
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

		clock-names = "xo", "cpu_clk";



		#freq-domains-cells = <1>

		#freq-domains-cells = <2>



	};

}