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Commit bfdef3b3 authored by Ben Dooks's avatar Ben Dooks
Browse files

ARM: hardware: fix endian-ness in <hardware/coresight.h> 



The <hardware/coresight.h> needs to take into account the endian-ness
of the processor when reading and writing data, so change to using
the readl/writel relaxed variants from the raw ones.

Signed-off-by: default avatarBen Dooks <ben.dooks@codethink.co.uk>
parent 0ab89d0b

arch/arm/include/asm/hardware/coresight.h

+4 −4
Original line number Diff line number Diff line
@@ -24,8 +24,8 @@ 
#define TRACER_TIMEOUT 10000



#define etm_writel(t, v, x) \

	(__raw_writel((v), (t)->etm_regs + (x)))

#define etm_readl(t, x) (__raw_readl((t)->etm_regs + (x)))

	(writel_relaxed((v), (t)->etm_regs + (x)))

#define etm_readl(t, x) (readl_relaxed((t)->etm_regs + (x)))



/* CoreSight Management Registers */

#define CSMR_LOCKACCESS 0xfb0
@@ -142,8 +142,8 @@ 
#define ETBFF_TRIGFL		BIT(10)



#define etb_writel(t, v, x) \

	(__raw_writel((v), (t)->etb_regs + (x)))

#define etb_readl(t, x) (__raw_readl((t)->etb_regs + (x)))

	(writel_relaxed((v), (t)->etb_regs + (x)))

#define etb_readl(t, x) (readl_relaxed((t)->etb_regs + (x)))



#define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0)

#define etm_unlock(t) \