Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit bee266a6 authored by Don Brace's avatar Don Brace Committed by James Bottomley
Browse files

hpsa: slightly optimize SA5_performant_completed 



Reviewed-by: default avatarScott Teel <scott.teel@pmcs.com>
Signed-off-by: default avatarDon Brace <don.brace@pmcs.com>
Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
parent 34f0c627

drivers/scsi/hpsa.h

+4 −4
Original line number Diff line number Diff line
@@ -412,19 +412,19 @@ static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) 
	unsigned long register_value = FIFO_EMPTY;



	/* msi auto clears the interrupt pending bit. */

	if (!(h->msi_vector || h->msix_vector)) {

	if (unlikely(!(h->msi_vector || h->msix_vector))) {

		/* flush the controller write of the reply queue by reading

		 * outbound doorbell status register.

		 */

		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);

		(void) readl(h->vaddr + SA5_OUTDB_STATUS);

		writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);

		/* Do a read in order to flush the write to the controller

		 * (as per spec.)

		 */

		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);

		(void) readl(h->vaddr + SA5_OUTDB_STATUS);

	}



	if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {

	if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) {

		register_value = rq->head[rq->current_entry];

		rq->current_entry++;

		atomic_dec(&h->commands_outstanding);