Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Unverified Commit bec2e6ac authored by Christoph Hellwig's avatar Christoph Hellwig Committed by Palmer Dabbelt
Browse files

RISC-V: add a definition for the SIE SEIE bit 



This mirrors the SIE_SSIE and SETE bits that are used in a similar
fashion.

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 4b40e9dd

arch/riscv/include/asm/csr.h

+1 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ 
/* Interrupt Enable and Interrupt Pending flags */

#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */

#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */

#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */



#define EXC_INST_MISALIGNED     0

#define EXC_INST_ACCESS         1