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Commit be15d65d authored by Kristoffer Ericson's avatar Kristoffer Ericson Committed by Paul Mundt
Browse files

sh: hd64461.h cleanup and added comments. 



Now that we dont have PIO mapping anymore we need to make sure we
got the correct value in our headers. Some well needed comments
have also been added.

Signed-off-by: default avatarKristoffer Ericson <kristoffer.ericson@gmail.com>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent bdf4fa53

include/asm-sh/hd64461.h

+219 −178
Original line number Original line Diff line number Diff line 
#ifndef __ASM_SH_HD64461

#ifndef __ASM_SH_HD64461

#define __ASM_SH_HD64461

#define __ASM_SH_HD64461

/*

/*

 *	$Id: hd64461.h,v 1.5 2004/03/16 00:07:51 lethal Exp $

 *	Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>

 *	Copyright (C) 2004 Paul Mundt

 *	Copyright (C) 2000 YAEGASHI Takeshi

 *	Copyright (C) 2000 YAEGASHI Takeshi

 *

 *		Hitachi HD64461 companion chip support

 *		Hitachi HD64461 companion chip support

 *	(please note manual reference 0x10000000 = 0xb0000000)

 */

 */





/* Constants for PCMCIA mappings */

/* Constants for PCMCIA mappings */

#define	HD64461_PCC_WINDOW	0x01000000

#define	HD64461_PCC_WINDOW	0x01000000





#define HD64461_PCC0_BASE	0xb8000000	/* area 6 */

/* Area 6 - Slot 0 - memory and/or IO card */

#define HD64461_PCC0_ATTR	(HD64461_PCC0_BASE)

#define	HD64461_PCC0_BASE	(CONFIG_HD64461_IOBASE + 0x8000000)

#define HD64461_PCC0_COMM	(HD64461_PCC0_BASE+HD64461_PCC_WINDOW)

#define	HD64461_PCC0_ATTR	(HD64461_PCC0_BASE)				/* 0xb80000000 */

#define HD64461_PCC0_IO		(HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)

#define	HD64461_PCC0_COMM	(HD64461_PCC0_BASE+HD64461_PCC_WINDOW)		/* 0xb90000000 */

#define	HD64461_PCC0_IO		(HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)	/* 0xba0000000 */





#define HD64461_PCC1_BASE	0xb4000000	/* area 5 */

/* Area 5 - Slot 1 - memory card only */

#define HD64461_PCC1_ATTR	(HD64461_PCC1_BASE)

#define	HD64461_PCC1_BASE	(CONFIG_HD64461_IOBASE + 0x4000000)

#define HD64461_PCC1_COMM	(HD64461_PCC1_BASE+HD64461_PCC_WINDOW)

#define	HD64461_PCC1_ATTR	(HD64461_PCC1_BASE)				/* 0xb4000000 */

#define	HD64461_PCC1_COMM	(HD64461_PCC1_BASE+HD64461_PCC_WINDOW)		/* 0xb5000000 */





#define HD64461_STBCR	0x10000

/* Standby Control Register for HD64461 */

#define	HD64461_STBCR			CONFIG_HD64461_IOBASE

#define	HD64461_STBCR_CKIO_STBY		0x2000

#define	HD64461_STBCR_CKIO_STBY		0x2000

#define	HD64461_STBCR_SAFECKE_IST	0x1000

#define	HD64461_STBCR_SAFECKE_IST	0x1000

#define	HD64461_STBCR_SLCKE_IST		0x0800

#define	HD64461_STBCR_SLCKE_IST		0x0800
@@ -34,76 +40,98 @@ 
#define	HD64461_STBCR_SIRST		0x0002

#define	HD64461_STBCR_SIRST		0x0002

#define	HD64461_STBCR_SURTST		0x0001

#define	HD64461_STBCR_SURTST		0x0001





#define HD64461_SYSCR	0x10002

/* System Configuration Register */

#define HD64461_SCPUCR	0x10004

#define	HD64461_SYSCR		(CONFIG_HD64461_IOBASE + 0x02)





#define HD64461_LCDCBAR		0x11000

/* CPU Data Bus Control Register */

#define HD64461_LCDCLOR		0x11002

#define	HD64461_SCPUCR		(CONFIG_HD64461_IOBASE + 0x04)

#define HD64461_LCDCCR		0x11004



#define HD64461_LCDCCR_STBACK	0x0400

/* Base Adress Register */

#define HD64461_LCDCCR_STREQ	0x0100

#define	HD64461_LCDCBAR		(CONFIG_HD64461_IOBASE + 0x1000)

#define HD64461_LCDCCR_MOFF	0x0080



#define HD64461_LCDCCR_REFSEL	0x0040

/* Line increment adress */

#define HD64461_LCDCCR_EPON	0x0020

#define	HD64461_LCDCLOR		(CONFIG_HD64461_IOBASE + 0x1002)

#define HD64461_LCDCCR_SPON	0x0010





/* Controls LCD controller */

#define	HD64461_LDR1		0x11010

#define	HD64461_LCDCCR		(CONFIG_HD64461_IOBASE + 0x1004)

#define	HD64461_LDR1_DON	0x01



#define	HD64461_LDR1_DINV	0x80

/* LCCDR control bits */



#define	HD64461_LCDCCR_STBACK	0x0400	/* Standby Back */

#define	HD64461_LDR2		0x11012

#define	HD64461_LCDCCR_STREQ	0x0100	/* Standby Request */

#define	HD64461_LDHNCR		0x11014

#define	HD64461_LCDCCR_MOFF	0x0080	/* Memory Off */

#define	HD64461_LDHNSR		0x11016

#define	HD64461_LCDCCR_REFSEL	0x0040	/* Refresh Select */

#define HD64461_LDVNTR		0x11018

#define	HD64461_LCDCCR_EPON	0x0020	/* End Power On */

#define HD64461_LDVNDR		0x1101a

#define	HD64461_LCDCCR_SPON	0x0010	/* Start Power On */

#define HD64461_LDVSPR		0x1101c



#define HD64461_LDR3		0x1101e

/* Controls LCD (1) */



#define	HD64461_LDR1		(CONFIG_HD64461_IOBASE + 0x1010)

#define HD64461_CPTWAR		0x11030

#define	HD64461_LDR1_DON	0x01	/* Display On */

#define HD64461_CPTWDR		0x11032

#define	HD64461_LDR1_DINV	0x80	/* Display Invert */

#define HD64461_CPTRAR		0x11034



#define HD64461_CPTRDR		0x11036

/* Controls LCD (2) */



#define	HD64461_LDR2		(CONFIG_HD64461_IOBASE + 0x1012)

#define HD64461_GRDOR		0x11040

#define	HD64461_LDHNCR		(CONFIG_HD64461_IOBASE + 0x1014)	/* Number of horizontal characters */

#define HD64461_GRSCR		0x11042

#define	HD64461_LDHNSR		(CONFIG_HD64461_IOBASE + 0x1016)	/* Specify output start position + width of CL1 */

#define HD64461_GRCFGR		0x11044

#define	HD64461_LDVNTR		(CONFIG_HD64461_IOBASE + 0x1018)	/* Specify total vertical lines */

#define HD64461_GRCFGR_ACCSTATUS		0x10

#define	HD64461_LDVNDR		(CONFIG_HD64461_IOBASE + 0x101a)	/* specify number of display vertical lines */

#define HD64461_GRCFGR_ACCRESET			0x08

#define	HD64461_LDVSPR		(CONFIG_HD64461_IOBASE + 0x101c)	/* specify vertical synchronization pos and AC nr */

#define HD64461_GRCFGR_ACCSTART_BITBLT	0x06



#define HD64461_GRCFGR_ACCSTART_LINE	0x04

/* Controls LCD (3) */

#define HD64461_GRCFGR_COLORDEPTH16		0x01

#define	HD64461_LDR3		(CONFIG_HD64461_IOBASE + 0x101e)





#define HD64461_LNSARH		0x11046

/* Palette Registers */

#define HD64461_LNSARL		0x11048

#define	HD64461_CPTWAR		(CONFIG_HD64461_IOBASE + 0x1030)	/* Color Palette Write Adress Register */

#define HD64461_LNAXLR		0x1104a

#define	HD64461_CPTWDR		(CONFIG_HD64461_IOBASE + 0x1032)	/* Color Palette Write Data Register */

#define HD64461_LNDGR		0x1104c

#define	HD64461_CPTRAR		(CONFIG_HD64461_IOBASE + 0x1034)	/* Color Palette Read Adress Register */

#define HD64461_LNAXR		0x1104e

#define	HD64461_CPTRDR		(CONFIG_HD64461_IOBASE + 0x1036)	/* Color Palette Read Data Register */

#define HD64461_LNERTR		0x11050



#define HD64461_LNMDR		0x11052

#define	HD64461_GRDOR		(CONFIG_HD64461_IOBASE + 0x1040)	/* Display Resolution Offset Register */

#define HD64461_BBTSSARH	0x11054

#define	HD64461_GRSCR		(CONFIG_HD64461_IOBASE + 0x1042)	/* Solid Color Register */

#define HD64461_BBTSSARL	0x11056

#define	HD64461_GRCFGR		(CONFIG_HD64461_IOBASE + 0x1044)	/* Accelerator Configuration Register */

#define HD64461_BBTDSARH	0x11058



#define HD64461_BBTDSARL	0x1105a

#define	HD64461_GRCFGR_ACCSTATUS	0x10	/* Accelerator Status */

#define HD64461_BBTDWR		0x1105c

#define	HD64461_GRCFGR_ACCRESET		0x08	/* Accelerator Reset */

#define HD64461_BBTDHR		0x1105e

#define	HD64461_GRCFGR_ACCSTART_BITBLT	0x06	/* Accelerator Start BITBLT */

#define HD64461_BBTPARH		0x11060

#define	HD64461_GRCFGR_ACCSTART_LINE	0x04	/* Accelerator Start Line Drawing */

#define HD64461_BBTPARL		0x11062

#define	HD64461_GRCFGR_COLORDEPTH16	0x01	/* Sets Colordepth 16 for Accelerator */

#define HD64461_BBTMARH		0x11064

#define	HD64461_GRCFGR_COLORDEPTH8	0x01	/* Sets Colordepth 8 for Accelerator */

#define HD64461_BBTMARL		0x11066



#define HD64461_BBTROPR		0x11068

/* Line Drawing Registers */

#define HD64461_BBTMDR		0x1106a

#define	HD64461_LNSARH		(CONFIG_HD64461_IOBASE + 0x1046)	/* Line Start Adress Register (H) */

#define	HD64461_LNSARL		(CONFIG_HD64461_IOBASE + 0x1048)	/* Line Start Adress Register (L) */

#define	HD64461_LNAXLR		(CONFIG_HD64461_IOBASE + 0x104a)	/* Axis Pixel Length Register */

#define	HD64461_LNDGR		(CONFIG_HD64461_IOBASE + 0x104c)	/* Diagonal Register */

#define	HD64461_LNAXR		(CONFIG_HD64461_IOBASE + 0x104e)	/* Axial Register */

#define	HD64461_LNERTR		(CONFIG_HD64461_IOBASE + 0x1050)	/* Start Error Term Register */

#define	HD64461_LNMDR		(CONFIG_HD64461_IOBASE + 0x1052)	/* Line Mode Register */



/* BitBLT Registers */

#define	HD64461_BBTSSARH	(CONFIG_HD64461_IOBASE + 0x1054)	/* Source Start Adress Register (H) */

#define	HD64461_BBTSSARL	(CONFIG_HD64461_IOBASE + 0x1056)	/* Source Start Adress Register (L) */

#define	HD64461_BBTDSARH	(CONFIG_HD64461_IOBASE + 0x1058)	/* Destination Start Adress Register (H) */

#define	HD64461_BBTDSARL	(CONFIG_HD64461_IOBASE + 0x105a)	/* Destination Start Adress Register (L) */

#define	HD64461_BBTDWR		(CONFIG_HD64461_IOBASE + 0x105c)	/* Destination Block Width Register */

#define	HD64461_BBTDHR		(CONFIG_HD64461_IOBASE + 0x105e)	/* Destination Block Height Register */

#define	HD64461_BBTPARH		(CONFIG_HD64461_IOBASE + 0x1060)	/* Pattern Start Adress Register (H) */

#define	HD64461_BBTPARL		(CONFIG_HD64461_IOBASE + 0x1062)	/* Pattern Start Adress Register (L) */

#define	HD64461_BBTMARH		(CONFIG_HD64461_IOBASE + 0x1064)	/* Mask Start Adress Register (H) */

#define	HD64461_BBTMARL		(CONFIG_HD64461_IOBASE + 0x1066)	/* Mask Start Adress Register (L) */

#define	HD64461_BBTROPR		(CONFIG_HD64461_IOBASE + 0x1068)	/* ROP Register */

#define	HD64461_BBTMDR		(CONFIG_HD64461_IOBASE + 0x106a)	/* BitBLT Mode Register */





/* PC Card Controller Registers */

/* PC Card Controller Registers */

#define HD64461_PCC0ISR         0x12000 /* socket 0 interface status */

/* Maps to Physical Area 6 */

#define HD64461_PCC0GCR         0x12002 /* socket 0 general control */

#define	HD64461_PCC0ISR		(CONFIG_HD64461_IOBASE + 0x2000)	/* socket 0 interface status */

#define HD64461_PCC0CSCR        0x12004 /* socket 0 card status change */

#define	HD64461_PCC0GCR		(CONFIG_HD64461_IOBASE + 0x2002)	/* socket 0 general control */

#define HD64461_PCC0CSCIER      0x12006 /* socket 0 card status change interrupt enable */

#define	HD64461_PCC0CSCR	(CONFIG_HD64461_IOBASE + 0x2004)	/* socket 0 card status change */

#define HD64461_PCC0SCR         0x12008 /* socket 0 software control */

#define	HD64461_PCC0CSCIER	(CONFIG_HD64461_IOBASE + 0x2006)	/* socket 0 card status change interrupt enable */

#define HD64461_PCC1ISR         0x12010 /* socket 1 interface status */

#define	HD64461_PCC0SCR		(CONFIG_HD64461_IOBASE + 0x2008)	/* socket 0 software control */

#define HD64461_PCC1GCR         0x12012 /* socket 1 general control */

/* Maps to Physical Area 5 */

#define HD64461_PCC1CSCR        0x12014 /* socket 1 card status change */

#define	HD64461_PCC1ISR		(CONFIG_HD64461_IOBASE + 0x2010)	/* socket 1 interface status */

#define HD64461_PCC1CSCIER      0x12016 /* socket 1 card status change interrupt enable */

#define	HD64461_PCC1GCR		(CONFIG_HD64461_IOBASE + 0x2012)	/* socket 1 general control */

#define HD64461_PCC1SCR         0x12018 /* socket 1 software control */

#define	HD64461_PCC1CSCR	(CONFIG_HD64461_IOBASE + 0x2014)	/* socket 1 card status change */

#define	HD64461_PCC1CSCIER	(CONFIG_HD64461_IOBASE + 0x2016)	/* socket 1 card status change interrupt enable */

#define	HD64461_PCC1SCR		(CONFIG_HD64461_IOBASE + 0x2018)	/* socket 1 software control */





/* PCC Interface Status Register */

/* PCC Interface Status Register */

#define	HD64461_PCCISR_READY		0x80	/* card ready */

#define	HD64461_PCCISR_READY		0x80	/* card ready */
@@ -160,31 +188,44 @@ 
#define	HD64461_PCCSCR_VCC1		0x02	/* voltage control pin 1 */

#define	HD64461_PCCSCR_VCC1		0x02	/* voltage control pin 1 */

#define	HD64461_PCCSCR_SWP		0x01	/* write protect */

#define	HD64461_PCCSCR_SWP		0x01	/* write protect */





#define HD64461_P0OCR           0x1202a

/* PCC0 Output Pins Control Register */

#define HD64461_P1OCR           0x1202c

#define	HD64461_P0OCR		(CONFIG_HD64461_IOBASE + 0x202a)

#define HD64461_PGCR            0x1202e





/* PCC1 Output Pins Control Register */

#define HD64461_GPACR		0x14000

#define	HD64461_P1OCR		(CONFIG_HD64461_IOBASE + 0x202c)

#define HD64461_GPBCR		0x14002



#define HD64461_GPCCR		0x14004

/* PC Card General Control Register */

#define HD64461_GPDCR		0x14006

#define	HD64461_PGCR		(CONFIG_HD64461_IOBASE + 0x202e)

#define HD64461_GPADR		0x14010



#define HD64461_GPBDR		0x14012

/* Port Control Registers */

#define HD64461_GPCDR		0x14014

#define	HD64461_GPACR		(CONFIG_HD64461_IOBASE + 0x4000)	/* Port A - Handles IRDA/TIMER */

#define HD64461_GPDDR		0x14016

#define	HD64461_GPBCR		(CONFIG_HD64461_IOBASE + 0x4002)	/* Port B - Handles UART */

#define HD64461_GPAICR		0x14020

#define	HD64461_GPCCR		(CONFIG_HD64461_IOBASE + 0x4004)	/* Port C - Handles PCMCIA 1 */

#define HD64461_GPBICR		0x14022

#define	HD64461_GPDCR		(CONFIG_HD64461_IOBASE + 0x4006)	/* Port D - Handles PCMCIA 1 */

#define HD64461_GPCICR		0x14024



#define HD64461_GPDICR		0x14026

/* Port Control Data Registers */

#define HD64461_GPAISR		0x14040

#define	HD64461_GPADR		(CONFIG_HD64461_IOBASE + 0x4010)	/* A */

#define HD64461_GPBISR		0x14042

#define	HD64461_GPBDR		(CONFIG_HD64461_IOBASE + 0x4012)	/* B */

#define HD64461_GPCISR		0x14044

#define	HD64461_GPCDR		(CONFIG_HD64461_IOBASE + 0x4014)	/* C */

#define HD64461_GPDISR		0x14046

#define	HD64461_GPDDR		(CONFIG_HD64461_IOBASE + 0x4016)	/* D */





#define HD64461_NIRR		0x15000

/* Interrupt Control Registers */

#define HD64461_NIMR		0x15002

#define	HD64461_GPAICR		(CONFIG_HD64461_IOBASE + 0x4020)	/* A */



#define	HD64461_GPBICR		(CONFIG_HD64461_IOBASE + 0x4022)	/* B */

#define HD64461_IRQBASE		64

#define	HD64461_GPCICR		(CONFIG_HD64461_IOBASE + 0x4024)	/* C */

#define	HD64461_GPDICR		(CONFIG_HD64461_IOBASE + 0x4026)	/* D */



/* Interrupt Status Registers */

#define	HD64461_GPAISR		(CONFIG_HD64461_IOBASE + 0x4040)	/* A */

#define	HD64461_GPBISR		(CONFIG_HD64461_IOBASE + 0x4042)	/* B */

#define	HD64461_GPCISR		(CONFIG_HD64461_IOBASE + 0x4044)	/* C */

#define	HD64461_GPDISR		(CONFIG_HD64461_IOBASE + 0x4046)	/* D */



/* Interrupt Request Register & Interrupt Mask Register */

#define	HD64461_NIRR		(CONFIG_HD64461_IOBASE + 0x5000)

#define	HD64461_NIMR		(CONFIG_HD64461_IOBASE + 0x5002)



#define	HD64461_IRQBASE		OFFCHIP_IRQ_BASE

#define	HD64461_IRQ_NUM		16

#define	HD64461_IRQ_NUM		16





#define	HD64461_IRQ_UART	(HD64461_IRQBASE+5)

#define	HD64461_IRQ_UART	(HD64461_IRQBASE+5)