clk: st: Adds divmux and prediv clock binding (be10afcd) · Commits · e / devices / android_kernel_oneplus_sm7250

Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt

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Original line number	Diff line number	Diff line
		Binding for a ST divider and multiplexer clock driver.

		This binding uses the common clock binding[1].
		Base address is located to the parent node. See clock binding[2]

		[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
		[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt

		Required properties:

		- compatible : shall be:
		"st,clkgena-divmux-c65-hs", "st,clkgena-divmux"
		"st,clkgena-divmux-c65-ls", "st,clkgena-divmux"
		"st,clkgena-divmux-c32-odf0", "st,clkgena-divmux"
		"st,clkgena-divmux-c32-odf1", "st,clkgena-divmux"
		"st,clkgena-divmux-c32-odf2", "st,clkgena-divmux"
		"st,clkgena-divmux-c32-odf3", "st,clkgena-divmux"

		- #clock-cells : From common clock binding; shall be set to 1.

		- clocks : From common clock binding

		- clock-output-names : From common clock binding.

		Example:

		clockgenA@fd345000 {
		reg = <0xfd345000 0xb50>;

		CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
		#clock-cells = <1>;
		compatible = "st,clkgena-divmux-c32-odf1",
		"st,clkgena-divmux";

		clocks = <&CLK_M_A1_OSC_PREDIV>,
		<&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
		<&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */

		clock-output-names = "CLK_M_RX_ICN_TS",
		"CLK_M_RX_ICN_VDP_0",
		"", /* Unused */
		"CLK_M_PRV_T1_BUS",
		"CLK_M_ICN_REG_12",
		"CLK_M_ICN_REG_10",
		"", /* Unused */
		"CLK_M_ICN_ST231";
		};
		};

Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt

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Original line number	Diff line number	Diff line
		Binding for a ST pre-divider clock driver.

		This binding uses the common clock binding[1].
		Base address is located to the parent node. See clock binding[2]

		[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
		[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt

		Required properties:

		- compatible : shall be:
		"st,clkgena-prediv-c65", "st,clkgena-prediv"
		"st,clkgena-prediv-c32", "st,clkgena-prediv"

		- #clock-cells : From common clock binding; shall be set to 0.

		- clocks : From common clock binding

		- clock-output-names : From common clock binding.

		Example:

		clockgenA@fd345000 {
		reg = <0xfd345000 0xb50>;

		CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
		#clock-cells = <0>;
		compatible = "st,clkgena-prediv-c32",
		"st,clkgena-prediv";

		clocks = <&CLK_SYSIN>;

		clock-output-names = "CLK_M_A2_OSC_PREDIV";
		};
		};

Documentation/devicetree/bindings/clock/st/st,clkgen.txt

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Original line number	Diff line number	Diff line
		Binding for a Clockgen hardware block found on
		certain STMicroelectronics consumer electronics SoC devices.

		A Clockgen node can contain pll, diviser or multiplexer nodes.

		We will find only the base address of the Clockgen, this base
		address is common of all subnode.

		clockgen_node {
		reg = <>;

		pll_node {
		...
		};

		prediv_node {
		...
		};

		divmux_node {
		...
		};

		quadfs_node {
		...
		};
		...
		};

		This binding uses the common clock binding[1].
		Each subnode should use the binding discribe in [2]..[4]

		[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
		[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
		[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
		[4] Documentation/devicetree/bindings/clock/st,quadfs.txt

		Required properties:
		- reg : A Base address and length of the register set.

		Example:

		clockgenA@fee62000 {

		reg = <0xfee62000 0xb48>;

		CLK_S_A0_PLL: CLK_S_A0_PLL {
		#clock-cells = <1>;
		compatible = "st,clkgena-plls-c65";

		clocks = <&CLK_SYSIN>;

		clock-output-names = "CLK_S_A0_PLL0_HS",
		"CLK_S_A0_PLL0_LS",
		"CLK_S_A0_PLL1";
		};

		CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
		#clock-cells = <0>;
		compatible = "st,clkgena-prediv-c65",
		"st,clkgena-prediv";

		clocks = <&CLK_SYSIN>;

		clock-output-names = "CLK_S_A0_OSC_PREDIV";
		};

		CLK_S_A0_HS: CLK_S_A0_HS {
		#clock-cells = <1>;
		compatible = "st,clkgena-divmux-c65-hs",
		"st,clkgena-divmux";

		clocks = <&CLK_S_A0_OSC_PREDIV>,
		<&CLK_S_A0_PLL 0>, /* PLL0 HS */
		<&CLK_S_A0_PLL 2>; /* PLL1 */

		clock-output-names = "CLK_S_FDMA_0",
		"CLK_S_FDMA_1",
		""; /* CLK_S_JIT_SENSE */
		/* Fourth output unused */
		};
		};