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Commit bdfef5be authored by David Dai's avatar David Dai
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dt-bindings: clock: add bindings for kona dispcc driver 



Add documentation for devicetree examples headers to help describe the
display clock driver for kona.

Change-Id: I1895f7b3903ec2e43ca8c349fb97ef98545088e6
Signed-off-by: default avatarDavid Dai <daidavid1@codeaurora.org>
parent 0d0eaa5f

Documentation/devicetree/bindings/clock/qcom,dispcc.txt

+23 −2
Original line number Diff line number Diff line
@@ -3,13 +3,23 @@ Qualcomm Technologies, Inc. Display Clock Controller Binding 


Required properties :



- compatible : shall contain "qcom,sdm845-dispcc"

- compatible : Shall contain one of the following:

		"qcom,kona-dispcc",

		"qcom,sdm845-dispcc"

- reg : shall contain base register location and length.

- vdd_mm-supply: phandle to the MM_CX rail that needs to be voted on behalf

of the clocks.

- clock-names: Shall contain "cfg_ahb_clk"

- clocks: phandle clock reference to the GCC AHB clock.

- #clock-cells : from common clock binding, shall contain 1.

- #reset-cells : from common reset binding, shall contain 1.

- #power-domain-cells : from generic power domain binding, shall contain 1.



Example:

Optional properties :



- reg-names: Address name. Must be "cc_base".



Examples:

	dispcc: clock-controller@af00000 {

		compatible = "qcom,sdm845-dispcc";

		reg = <0xaf00000 0x100000>;
@@ -17,3 +27,14 @@ Example: 
		#reset-cells = <1>;

		#power-domain-cells = <1>;

	};



	clock_dispcc: qcom,dispcc@af00000 {

		compatible = "qcom,kona-dispcc";

		reg = <0xaf00000 0x20000>;

		reg-names = "cc_base";

		vdd_mm-supply = <&VDD_MMCX_LEVEL>;

		clock-names = "cfg_ahb_clk";

		clocks = <&clock_gcc GCC_DISP_AHB_CLK>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

include/dt-bindings/clock/qcom,dispcc-kona.h

+84 −59
Original line number Diff line number Diff line
@@ -4,65 +4,90 @@ 
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_KONA_H

#define _DT_BINDINGS_CLK_QCOM_DISP_CC_KONA_H



#define DISP_CC_MDSS_AHB_CLK					0

#define DISP_CC_MDSS_AHB_CLK_SRC				1

#define DISP_CC_MDSS_BYTE0_CLK					2

#define DISP_CC_MDSS_BYTE0_CLK_SRC				3

#define DISP_CC_MDSS_BYTE0_INTF_CLK				4

#define DISP_CC_MDSS_BYTE1_CLK					5

#define DISP_CC_MDSS_BYTE1_CLK_SRC				6

#define DISP_CC_MDSS_BYTE1_INTF_CLK				7

#define DISP_CC_MDSS_DP_AUX1_CLK				8

#define DISP_CC_MDSS_DP_AUX1_CLK_SRC				9

#define DISP_CC_MDSS_DP_AUX_CLK					10

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				11

#define DISP_CC_MDSS_DP_CRYPTO1_CLK				12

#define DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC				13

#define DISP_CC_MDSS_DP_CRYPTO_CLK				14

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				15

#define DISP_CC_MDSS_DP_LINK1_CLK				16

#define DISP_CC_MDSS_DP_LINK1_CLK_SRC				17

#define DISP_CC_MDSS_DP_LINK1_INTF_CLK				18

#define DISP_CC_MDSS_DP_LINK_CLK				19

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				20

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				21

#define DISP_CC_MDSS_DP_PIXEL1_CLK				22

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				23

#define DISP_CC_MDSS_DP_PIXEL2_CLK				24

#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC				25

#define DISP_CC_MDSS_DP_PIXEL_CLK				26

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				27

#define DISP_CC_MDSS_EDP_AUX_CLK				28

#define DISP_CC_MDSS_EDP_AUX_CLK_SRC				29

#define DISP_CC_MDSS_EDP_GTC_CLK				30

#define DISP_CC_MDSS_EDP_GTC_CLK_SRC				31

#define DISP_CC_MDSS_EDP_LINK_CLK				32

#define DISP_CC_MDSS_EDP_LINK_CLK_SRC				33

#define DISP_CC_MDSS_EDP_LINK_INTF_CLK				34

#define DISP_CC_MDSS_EDP_PIXEL_CLK				35

#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC				36

#define DISP_CC_MDSS_ESC0_CLK					37

#define DISP_CC_MDSS_ESC0_CLK_SRC				38

#define DISP_CC_MDSS_ESC1_CLK					39

#define DISP_CC_MDSS_ESC1_CLK_SRC				40

#define DISP_CC_MDSS_MDP_CLK					41

#define DISP_CC_MDSS_MDP_CLK_SRC				42

#define DISP_CC_MDSS_MDP_LUT_CLK				43

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				44

#define DISP_CC_MDSS_PCLK0_CLK					45

#define DISP_CC_MDSS_PCLK0_CLK_SRC				46

#define DISP_CC_MDSS_PCLK1_CLK					47

#define DISP_CC_MDSS_PCLK1_CLK_SRC				48

#define DISP_CC_MDSS_ROT_CLK					49

#define DISP_CC_MDSS_ROT_CLK_SRC				50

#define DISP_CC_MDSS_RSCC_AHB_CLK				51

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				52

#define DISP_CC_MDSS_VSYNC_CLK					53

#define DISP_CC_MDSS_VSYNC_CLK_SRC				54

#define DISP_CC_PLL0						55

#define DISP_CC_PLL1						56

#define DISP_CC_XO_CLK						57

#define DISP_CC_XO_CLK_SRC					58

#define DISP_CC_DEBUG_CLK					0

#define DISP_CC_MDSS_AHB_CLK					1

#define DISP_CC_MDSS_AHB_CLK_SRC				2

#define DISP_CC_MDSS_BYTE0_CLK					3

#define DISP_CC_MDSS_BYTE0_CLK_SRC				4

#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				5

#define DISP_CC_MDSS_BYTE0_INTF_CLK				6

#define DISP_CC_MDSS_BYTE1_CLK					7

#define DISP_CC_MDSS_BYTE1_CLK_SRC				8

#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				9

#define DISP_CC_MDSS_BYTE1_INTF_CLK				10

#define DISP_CC_MDSS_DP_AUX1_CLK				11

#define DISP_CC_MDSS_DP_AUX1_CLK_SRC				12

#define DISP_CC_MDSS_DP_AUX_CLK					13

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				14

#define DISP_CC_MDSS_DP_CRYPTO1_CLK				15

#define DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC				16

#define DISP_CC_MDSS_DP_CRYPTO_CLK				17

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				18

#define DISP_CC_MDSS_DP_LINK1_CLK				19

#define DISP_CC_MDSS_DP_LINK1_CLK_SRC				20

#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC			21

#define DISP_CC_MDSS_DP_LINK1_INTF_CLK				22

#define DISP_CC_MDSS_DP_LINK_CLK				23

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				24

#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC			25

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				26

#define DISP_CC_MDSS_DP_PIXEL1_CLK				27

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				28

#define DISP_CC_MDSS_DP_PIXEL2_CLK				29

#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC				30

#define DISP_CC_MDSS_DP_PIXEL_CLK				31

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				32

#define DISP_CC_MDSS_EDP_AUX_CLK				33

#define DISP_CC_MDSS_EDP_AUX_CLK_SRC				34

#define DISP_CC_MDSS_EDP_GTC_CLK				35

#define DISP_CC_MDSS_EDP_GTC_CLK_SRC				36

#define DISP_CC_MDSS_EDP_LINK_CLK				37

#define DISP_CC_MDSS_EDP_LINK_CLK_SRC				38

#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC			39

#define DISP_CC_MDSS_EDP_LINK_INTF_CLK				40

#define DISP_CC_MDSS_EDP_PIXEL_CLK				41

#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC				42

#define DISP_CC_MDSS_ESC0_CLK					43

#define DISP_CC_MDSS_ESC0_CLK_SRC				44

#define DISP_CC_MDSS_ESC1_CLK					45

#define DISP_CC_MDSS_ESC1_CLK_SRC				46

#define DISP_CC_MDSS_MDP_CLK					47

#define DISP_CC_MDSS_MDP_CLK_SRC				48

#define DISP_CC_MDSS_MDP_LUT_CLK				49

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				50

#define DISP_CC_MDSS_PCLK0_CLK					51

#define DISP_CC_MDSS_PCLK0_CLK_SRC				52

#define DISP_CC_MDSS_PCLK1_CLK					53

#define DISP_CC_MDSS_PCLK1_CLK_SRC				54

#define DISP_CC_MDSS_ROT_CLK					55

#define DISP_CC_MDSS_ROT_CLK_SRC				56

#define DISP_CC_MDSS_RSCC_AHB_CLK				57

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				58

#define DISP_CC_MDSS_SPDM_DEBUG_CLK				59

#define DISP_CC_MDSS_SPDM_DP_CRYPTO_CLK				60

#define DISP_CC_MDSS_SPDM_DP_CRYPTO_DIV_CLK_SRC			61

#define DISP_CC_MDSS_SPDM_DP_PIXEL1_CLK				62

#define DISP_CC_MDSS_SPDM_DP_PIXEL1_DIV_CLK_SRC			63

#define DISP_CC_MDSS_SPDM_DP_PIXEL_CLK				64

#define DISP_CC_MDSS_SPDM_DP_PIXEL_DIV_CLK_SRC			65

#define DISP_CC_MDSS_SPDM_MDP_CLK				66

#define DISP_CC_MDSS_SPDM_MDP_DIV_CLK_SRC			67

#define DISP_CC_MDSS_SPDM_PCLK0_CLK				68

#define DISP_CC_MDSS_SPDM_PCLK0_DIV_CLK_SRC			69

#define DISP_CC_MDSS_SPDM_PCLK1_CLK				70

#define DISP_CC_MDSS_SPDM_PCLK1_DIV_CLK_SRC			71

#define DISP_CC_MDSS_SPDM_ROT_CLK				72

#define DISP_CC_MDSS_SPDM_ROT_DIV_CLK_SRC			73

#define DISP_CC_MDSS_VSYNC_CLK					74

#define DISP_CC_MDSS_VSYNC_CLK_SRC				75

#define DISP_CC_PLL0						76

#define DISP_CC_PLL1						77

#define DISP_CC_PLL_TEST_CLK					78

#define DISP_CC_PLL_TEST_DIV_CLK_SRC				79

#define DISP_CC_SLEEP_CLK					80

#define DISP_CC_SLEEP_CLK_SRC					81

#define DISP_CC_XO_CLK						82

#define DISP_CC_XO_CLK_SRC					83



#define MDSS_CORE_GDSC						0