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Commit bded18c2 authored by Giuseppe CAVALLARO's avatar Giuseppe CAVALLARO Committed by David S. Miller
Browse files

stmmac: fixed dma lib build when turn-on the debug option 



This patch fixes a compilation error when build the
dwmac_lib with the DEBUG option enabled.

Signed-off-by: default avatarGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 0e10b33a

drivers/net/stmmac/dwmac_lib.c

+14 −14
Original line number Diff line number Diff line
@@ -26,9 +26,9 @@ 


#undef DWMAC_DMA_DEBUG

#ifdef DWMAC_DMA_DEBUG

#define DBG(fmt, args...)  printk(fmt, ## args)

#define DWMAC_LIB_DBG(fmt, args...)  printk(fmt, ## args)

#else

#define DBG(fmt, args...)  do { } while (0)

#define DWMAC_LIB_DBG(fmt, args...)  do { } while (0)

#endif



/* CSR1 enables the transmit DMA to check for new descriptor */
@@ -152,7 +152,7 @@ int dwmac_dma_interrupt(void __iomem *ioaddr, 
	/* read the status register (CSR5) */

	u32 intr_status = readl(ioaddr + DMA_STATUS);



	DBG(INFO, "%s: [CSR5: 0x%08x]\n", __func__, intr_status);

	DWMAC_LIB_DBG(KERN_INFO "%s: [CSR5: 0x%08x]\n", __func__, intr_status);

#ifdef DWMAC_DMA_DEBUG

	/* It displays the DMA process states (CSR5 register) */

	show_tx_process_state(intr_status);
@@ -160,43 +160,43 @@ int dwmac_dma_interrupt(void __iomem *ioaddr, 
#endif

	/* ABNORMAL interrupts */

	if (unlikely(intr_status & DMA_STATUS_AIS)) {

		DBG(INFO, "CSR5[15] DMA ABNORMAL IRQ: ");

		DWMAC_LIB_DBG(KERN_INFO "CSR5[15] DMA ABNORMAL IRQ: ");

		if (unlikely(intr_status & DMA_STATUS_UNF)) {

			DBG(INFO, "transmit underflow\n");

			DWMAC_LIB_DBG(KERN_INFO "transmit underflow\n");

			ret = tx_hard_error_bump_tc;

			x->tx_undeflow_irq++;

		}

		if (unlikely(intr_status & DMA_STATUS_TJT)) {

			DBG(INFO, "transmit jabber\n");

			DWMAC_LIB_DBG(KERN_INFO "transmit jabber\n");

			x->tx_jabber_irq++;

		}

		if (unlikely(intr_status & DMA_STATUS_OVF)) {

			DBG(INFO, "recv overflow\n");

			DWMAC_LIB_DBG(KERN_INFO "recv overflow\n");

			x->rx_overflow_irq++;

		}

		if (unlikely(intr_status & DMA_STATUS_RU)) {

			DBG(INFO, "receive buffer unavailable\n");

			DWMAC_LIB_DBG(KERN_INFO "receive buffer unavailable\n");

			x->rx_buf_unav_irq++;

		}

		if (unlikely(intr_status & DMA_STATUS_RPS)) {

			DBG(INFO, "receive process stopped\n");

			DWMAC_LIB_DBG(KERN_INFO "receive process stopped\n");

			x->rx_process_stopped_irq++;

		}

		if (unlikely(intr_status & DMA_STATUS_RWT)) {

			DBG(INFO, "receive watchdog\n");

			DWMAC_LIB_DBG(KERN_INFO "receive watchdog\n");

			x->rx_watchdog_irq++;

		}

		if (unlikely(intr_status & DMA_STATUS_ETI)) {

			DBG(INFO, "transmit early interrupt\n");

			DWMAC_LIB_DBG(KERN_INFO "transmit early interrupt\n");

			x->tx_early_irq++;

		}

		if (unlikely(intr_status & DMA_STATUS_TPS)) {

			DBG(INFO, "transmit process stopped\n");

			DWMAC_LIB_DBG(KERN_INFO "transmit process stopped\n");

			x->tx_process_stopped_irq++;

			ret = tx_hard_error;

		}

		if (unlikely(intr_status & DMA_STATUS_FBI)) {

			DBG(INFO, "fatal bus error\n");

			DWMAC_LIB_DBG(KERN_INFO "fatal bus error\n");

			x->fatal_bus_error_irq++;

			ret = tx_hard_error;

		}
@@ -215,7 +215,7 @@ int dwmac_dma_interrupt(void __iomem *ioaddr, 
	/* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */

	writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);



	DBG(INFO, "\n\n");

	DWMAC_LIB_DBG(KERN_INFO "\n\n");

	return ret;

}