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Commit bdb8bfc6 authored by Archit Taneja's avatar Archit Taneja Committed by Tomi Valkeinen
Browse files

omapdss: HDMI: Clean up the header files 



Keep only OMAP4 HDMI core block related structs and enums in ti_hdmi_4xxx_ip.h,
move the rest to ti_hdmi.h. This holds all library specific data which will be
shared between OMAP4 and OMAP5/DRA7x HDMI encoder drivers.

Move the duplicate register read/write/wait_for_bit_change functions in the hdmi
library files to ti_hdmi.h

Signed-off-by: default avatarArchit Taneja <archit@ti.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
parent 275cfa1a

drivers/video/omap2/dss/hdmi_phy.c

+0 −31
Original line number Original line Diff line number Diff line
@@ -9,7 +9,6 @@ 
 */

 */





#include <linux/kernel.h>

#include <linux/kernel.h>

#include <linux/delay.h>

#include <linux/err.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/io.h>

#include <linux/platform_device.h>

#include <linux/platform_device.h>
@@ -17,40 +16,10 @@ 




#include "dss.h"

#include "dss.h"

#include "ti_hdmi.h"

#include "ti_hdmi.h"

#include "ti_hdmi_4xxx_ip.h"





#define HDMI_IRQ_LINK_CONNECT		(1 << 25)

#define HDMI_IRQ_LINK_CONNECT		(1 << 25)

#define HDMI_IRQ_LINK_DISCONNECT	(1 << 26)

#define HDMI_IRQ_LINK_DISCONNECT	(1 << 26)





static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx,

		u32 val)

{

	__raw_writel(val, base_addr + idx);

}



static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx)

{

	return __raw_readl(base_addr + idx);

}



#define REG_FLD_MOD(base, idx, val, start, end) \

	hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\

							val, start, end))

#define REG_GET(base, idx, start, end) \

	FLD_GET(hdmi_read_reg(base, idx), start, end)



static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,

		const u16 idx, int b2, int b1, u32 val)

{

	u32 t = 0;

	while (val != REG_GET(base_addr, idx, b2, b1)) {

		udelay(1);

		if (t++ > 10000)

			return !val;

	}

	return val;

}



void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s)

void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s)

{

{

#define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\

#define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\

drivers/video/omap2/dss/hdmi_pll.c

+0 −31
Original line number Original line Diff line number Diff line
@@ -10,7 +10,6 @@ 




#include <linux/kernel.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/module.h>

#include <linux/delay.h>

#include <linux/err.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/io.h>

#include <linux/platform_device.h>

#include <linux/platform_device.h>
@@ -18,40 +17,10 @@ 




#include "dss.h"

#include "dss.h"

#include "ti_hdmi.h"

#include "ti_hdmi.h"

#include "ti_hdmi_4xxx_ip.h"





#define HDMI_DEFAULT_REGN 16

#define HDMI_DEFAULT_REGN 16

#define HDMI_DEFAULT_REGM2 1

#define HDMI_DEFAULT_REGM2 1





static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx,

		u32 val)

{

	__raw_writel(val, base_addr + idx);

}



static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx)

{

	return __raw_readl(base_addr + idx);

}



#define REG_FLD_MOD(base, idx, val, start, end) \

	hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\

							val, start, end))

#define REG_GET(base, idx, start, end) \

	FLD_GET(hdmi_read_reg(base, idx), start, end)



static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,

		const u16 idx, int b2, int b1, u32 val)

{

	u32 t = 0;

	while (val != REG_GET(base_addr, idx, b2, b1)) {

		udelay(1);

		if (t++ > 10000)

			return !val;

	}

	return val;

}



void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)

void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)

{

{

#define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\

#define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\

drivers/video/omap2/dss/hdmi_wp.c

+0 −31
Original line number Original line Diff line number Diff line
@@ -9,7 +9,6 @@ 
 */

 */





#include <linux/kernel.h>

#include <linux/kernel.h>

#include <linux/delay.h>

#include <linux/err.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/io.h>

#include <linux/platform_device.h>

#include <linux/platform_device.h>
@@ -17,36 +16,6 @@ 




#include "dss.h"

#include "dss.h"

#include "ti_hdmi.h"

#include "ti_hdmi.h"

#include "ti_hdmi_4xxx_ip.h"



static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx,

		u32 val)

{

	__raw_writel(val, base_addr + idx);

}



static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx)

{

	return __raw_readl(base_addr + idx);

}



#define REG_FLD_MOD(base, idx, val, start, end) \

	hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\

							val, start, end))

#define REG_GET(base, idx, start, end) \

	FLD_GET(hdmi_read_reg(base, idx), start, end)



static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,

		const u16 idx, int b2, int b1, u32 val)

{

	u32 t = 0;

	while (val != REG_GET(base_addr, idx, b2, b1)) {

		udelay(1);

		if (t++ > 10000)

			return !val;

	}

	return val;

}





void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)

void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)

{

{

drivers/video/omap2/dss/ti_hdmi.h

+170 −0
Original line number Original line Diff line number Diff line
@@ -21,7 +21,52 @@ 
#ifndef _TI_HDMI_H

#ifndef _TI_HDMI_H

#define _TI_HDMI_H

#define _TI_HDMI_H





#include <linux/delay.h>

#include <linux/io.h>

#include <linux/platform_device.h>

#include <linux/platform_device.h>

#include <video/omapdss.h>



#include "dss.h"



/* HDMI Wrapper */



#define HDMI_WP_REVISION			0x0

#define HDMI_WP_SYSCONFIG			0x10

#define HDMI_WP_IRQSTATUS_RAW			0x24

#define HDMI_WP_IRQSTATUS			0x28

#define HDMI_WP_IRQENABLE_SET			0x2C

#define HDMI_WP_IRQENABLE_CLR			0x30

#define HDMI_WP_IRQWAKEEN			0x34

#define HDMI_WP_PWR_CTRL			0x40

#define HDMI_WP_DEBOUNCE			0x44

#define HDMI_WP_VIDEO_CFG			0x50

#define HDMI_WP_VIDEO_SIZE			0x60

#define HDMI_WP_VIDEO_TIMING_H			0x68

#define HDMI_WP_VIDEO_TIMING_V			0x6C

#define HDMI_WP_WP_CLK				0x70

#define HDMI_WP_AUDIO_CFG			0x80

#define HDMI_WP_AUDIO_CFG2			0x84

#define HDMI_WP_AUDIO_CTRL			0x88

#define HDMI_WP_AUDIO_DATA			0x8C



/* HDMI PLL */



#define PLLCTRL_PLL_CONTROL			0x0

#define PLLCTRL_PLL_STATUS			0x4

#define PLLCTRL_PLL_GO				0x8

#define PLLCTRL_CFG1				0xC

#define PLLCTRL_CFG2				0x10

#define PLLCTRL_CFG3				0x14

#define PLLCTRL_SSC_CFG1			0x18

#define PLLCTRL_SSC_CFG2			0x1C

#define PLLCTRL_CFG4				0x20



/* HDMI PHY */



#define HDMI_TXPHY_TX_CTRL			0x0

#define HDMI_TXPHY_DIGITAL_CTRL			0x4

#define HDMI_TXPHY_POWER_CTRL			0x8

#define HDMI_TXPHY_PAD_CFG_CTRL			0xC





enum hdmi_pll_pwr {

enum hdmi_pll_pwr {

	HDMI_PLLPWRCMD_ALLOFF = 0,

	HDMI_PLLPWRCMD_ALLOFF = 0,
@@ -98,6 +143,75 @@ enum hdmi_audio_blk_strt_end_sig { 
	HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1

	HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1

};

};





enum hdmi_core_audio_layout {

	HDMI_AUDIO_LAYOUT_2CH = 0,

	HDMI_AUDIO_LAYOUT_8CH = 1

};



enum hdmi_core_cts_mode {

	HDMI_AUDIO_CTS_MODE_HW = 0,

	HDMI_AUDIO_CTS_MODE_SW = 1

};



enum hdmi_audio_mclk_mode {

	HDMI_AUDIO_MCLK_128FS = 0,

	HDMI_AUDIO_MCLK_256FS = 1,

	HDMI_AUDIO_MCLK_384FS = 2,

	HDMI_AUDIO_MCLK_512FS = 3,

	HDMI_AUDIO_MCLK_768FS = 4,

	HDMI_AUDIO_MCLK_1024FS = 5,

	HDMI_AUDIO_MCLK_1152FS = 6,

	HDMI_AUDIO_MCLK_192FS = 7

};



/* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */

enum hdmi_core_infoframe {

	HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,

	HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,

	HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,

	HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,

	HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON =  1,

	HDMI_INFOFRAME_AVI_DB1B_NO = 0,

	HDMI_INFOFRAME_AVI_DB1B_VERT = 1,

	HDMI_INFOFRAME_AVI_DB1B_HORI = 2,

	HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,

	HDMI_INFOFRAME_AVI_DB1S_0 = 0,

	HDMI_INFOFRAME_AVI_DB1S_1 = 1,

	HDMI_INFOFRAME_AVI_DB1S_2 = 2,

	HDMI_INFOFRAME_AVI_DB2C_NO = 0,

	HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,

	HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,

	HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,

	HDMI_INFOFRAME_AVI_DB2M_NO = 0,

	HDMI_INFOFRAME_AVI_DB2M_43 = 1,

	HDMI_INFOFRAME_AVI_DB2M_169 = 2,

	HDMI_INFOFRAME_AVI_DB2R_SAME = 8,

	HDMI_INFOFRAME_AVI_DB2R_43 = 9,

	HDMI_INFOFRAME_AVI_DB2R_169 = 10,

	HDMI_INFOFRAME_AVI_DB2R_149 = 11,

	HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,

	HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,

	HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,

	HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,

	HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,

	HDMI_INFOFRAME_AVI_DB3Q_LR = 1,

	HDMI_INFOFRAME_AVI_DB3Q_FR = 2,

	HDMI_INFOFRAME_AVI_DB3SC_NO = 0,

	HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,

	HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,

	HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,

	HDMI_INFOFRAME_AVI_DB5PR_NO = 0,

	HDMI_INFOFRAME_AVI_DB5PR_2 = 1,

	HDMI_INFOFRAME_AVI_DB5PR_3 = 2,

	HDMI_INFOFRAME_AVI_DB5PR_4 = 3,

	HDMI_INFOFRAME_AVI_DB5PR_5 = 4,

	HDMI_INFOFRAME_AVI_DB5PR_6 = 5,

	HDMI_INFOFRAME_AVI_DB5PR_7 = 6,

	HDMI_INFOFRAME_AVI_DB5PR_8 = 7,

	HDMI_INFOFRAME_AVI_DB5PR_9 = 8,

	HDMI_INFOFRAME_AVI_DB5PR_10 = 9,

};



struct hdmi_cm {

struct hdmi_cm {

	int	code;

	int	code;

	int	mode;

	int	mode;
@@ -143,6 +257,33 @@ struct hdmi_audio_dma { 
	u16				fifo_threshold;

	u16				fifo_threshold;

};

};





struct hdmi_core_audio_i2s_config {

	u8 in_length_bits;

	u8 justification;

	u8 sck_edge_mode;

	u8 vbit;

	u8 direction;

	u8 shift;

	u8 active_sds;

};



struct hdmi_core_audio_config {

	struct hdmi_core_audio_i2s_config	i2s_cfg;

	struct snd_aes_iec958			*iec60958_cfg;

	bool					fs_override;

	u32					n;

	u32					cts;

	u32					aud_par_busclk;

	enum hdmi_core_audio_layout		layout;

	enum hdmi_core_cts_mode			cts_mode;

	bool					use_mclk;

	enum hdmi_audio_mclk_mode		mclk_mode;

	bool					en_acr_pkt;

	bool					en_dsd_audio;

	bool					en_parallel_aud_input;

	bool					en_spdif;

};



/*

/*

 * Refer to section 8.2 in HDMI 1.3 specification for

 * Refer to section 8.2 in HDMI 1.3 specification for

 * details about infoframe databytes

 * details about infoframe databytes
@@ -206,6 +347,35 @@ struct hdmi_core_data { 
	struct hdmi_core_infoframe_avi avi_cfg;

	struct hdmi_core_infoframe_avi avi_cfg;

};

};





static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx,

		u32 val)

{

	__raw_writel(val, base_addr + idx);

}



static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx)

{

	return __raw_readl(base_addr + idx);

}



#define REG_FLD_MOD(base, idx, val, start, end) \

	hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\

							val, start, end))

#define REG_GET(base, idx, start, end) \

	FLD_GET(hdmi_read_reg(base, idx), start, end)



static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,

		const u16 idx, int b2, int b1, u32 val)

{

	u32 t = 0;

	while (val != REG_GET(base_addr, idx, b2, b1)) {

		udelay(1);

		if (t++ > 10000)

			return !val;

	}

	return val;

}



/* HDMI wrapper funcs */

/* HDMI wrapper funcs */

int hdmi_wp_video_start(struct hdmi_wp_data *wp);

int hdmi_wp_video_start(struct hdmi_wp_data *wp);

void hdmi_wp_video_stop(struct hdmi_wp_data *wp);

void hdmi_wp_video_stop(struct hdmi_wp_data *wp);

drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c

+0 −31
Original line number Original line Diff line number Diff line
@@ -35,41 +35,10 @@ 
#endif

#endif





#include "ti_hdmi_4xxx_ip.h"

#include "ti_hdmi_4xxx_ip.h"

#include "dss.h"

#include "dss_features.h"

#include "dss_features.h"





#define HDMI_CORE_AV		0x500

#define HDMI_CORE_AV		0x500





static inline void hdmi_write_reg(void __iomem *base_addr,

				const u16 idx, u32 val)

{

	__raw_writel(val, base_addr + idx);

}



static inline u32 hdmi_read_reg(void __iomem *base_addr,

				const u16 idx)

{

	return __raw_readl(base_addr + idx);

}



#define REG_FLD_MOD(base, idx, val, start, end) \

	hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\

							val, start, end))

#define REG_GET(base, idx, start, end) \

	FLD_GET(hdmi_read_reg(base, idx), start, end)



static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,

		const u16 idx, int b2, int b1, u32 val)

{

	u32 t = 0;

	while (val != REG_GET(base_addr, idx, b2, b1)) {

		udelay(1);

		if (t++ > 10000)

			return !val;

	}

	return val;

}



static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core)

static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core)

{

{

	return core->base + HDMI_CORE_AV;

	return core->base + HDMI_CORE_AV;