Merge branch 'linus' into perf/core, to pick up fixes

                Returns 1 if the psl timebase register is synchronized

                with the core timebase register, 0 otherwise.

Users:          https://github.com/ibm-capi/libcxl

What:           /sys/class/cxl/<card>/tunneled_ops_supported

Date:           May 2018

Contact:        linuxppc-dev@lists.ozlabs.org

Description:    read only

                Returns 1 if tunneled operations are supported in capi mode,

                0 otherwise.

Users:          https://github.com/ibm-capi/libcxl

		/sys/devices/system/cpu/vulnerabilities/meltdown

		/sys/devices/system/cpu/vulnerabilities/spectre_v1

		/sys/devices/system/cpu/vulnerabilities/spectre_v2

		/sys/devices/system/cpu/vulnerabilities/spec_store_bypass

Date:		January 2018

Contact:	Linux kernel mailing list <linux-kernel@vger.kernel.org>

Description:	Information about CPU vulnerabilities

			allow data leaks with this option, which is equivalent

			to spectre_v2=off.

	nospec_store_bypass_disable

			[HW] Disable all mitigations for the Speculative Store Bypass vulnerability

	noxsave		[BUGS=X86] Disables x86 extended register state save

			and restore using xsave. The kernel will fallback to

			enabling legacy floating-point and sse state.

			Not specifying this option is equivalent to

			spectre_v2=auto.

	spec_store_bypass_disable=

			[HW] Control Speculative Store Bypass (SSB) Disable mitigation

			(Speculative Store Bypass vulnerability)

			Certain CPUs are vulnerable to an exploit against a

			a common industry wide performance optimization known

			as "Speculative Store Bypass" in which recent stores

			to the same memory location may not be observed by

			later loads during speculative execution. The idea

			is that such stores are unlikely and that they can

			be detected prior to instruction retirement at the

			end of a particular speculation execution window.

			In vulnerable processors, the speculatively forwarded

			store can be used in a cache side channel attack, for

			example to read memory to which the attacker does not

			directly have access (e.g. inside sandboxed code).

			This parameter controls whether the Speculative Store

			Bypass optimization is used.

			on      - Unconditionally disable Speculative Store Bypass

			off     - Unconditionally enable Speculative Store Bypass

			auto    - Kernel detects whether the CPU model contains an

				  implementation of Speculative Store Bypass and

				  picks the most appropriate mitigation. If the

				  CPU is not vulnerable, "off" is selected. If the

				  CPU is vulnerable the default mitigation is

				  architecture and Kconfig dependent. See below.

			prctl   - Control Speculative Store Bypass per thread

				  via prctl. Speculative Store Bypass is enabled

				  for a process by default. The state of the control

				  is inherited on fork.

			seccomp - Same as "prctl" above, but all seccomp threads

				  will disable SSB unless they explicitly opt out.

			Not specifying this option is equivalent to

			spec_store_bypass_disable=auto.

			Default mitigations:

			X86:	If CONFIG_SECCOMP=y "seccomp", otherwise "prctl"

	spia_io_base=	[HW,MTD]

	spia_fio_base=

	spia_pedr=

	- main controller clock (for both armada-375-pp2 and armada-7k-pp2)

	- GOP clock (for both armada-375-pp2 and armada-7k-pp2)

	- MG clock (only for armada-7k-pp2)

	- MG Core clock (only for armada-7k-pp2)

	- AXI clock (only for armada-7k-pp2)

- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk"

  and "axi_clk" (the 2 latter only for armada-7k-pp2).

- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk",

  "mg_core_clk" and "axi_clk" (the 3 latter only for armada-7k-pp2).

The ethernet ports are represented by subnodes. At least one port is

required.

	compatible = "marvell,armada-7k-pp22";

	reg = <0x0 0x100000>, <0x129000 0xb000>;

	clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,

		 <&cpm_syscon0 1 5>, <&cpm_syscon0 1 18>;

	clock-names = "pp_clk", "gop_clk", "gp_clk", "axi_clk";

		 <&cpm_syscon0 1 5>, <&cpm_syscon0 1 6>, <&cpm_syscon0 1 18>;

	clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk";

	eth0: eth0 {

		interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,

      - txd2-skew-ps : Skew control of TX data 2 pad

      - txd3-skew-ps : Skew control of TX data 3 pad

    - micrel,force-master:

        Boolean, force phy to master mode. Only set this option if the phy

        reference clock provided at CLK125_NDO pin is used as MAC reference

        clock because the clock jitter in slave mode is to high (errata#2).

        Attention: The link partner must be configurable as slave otherwise

        no link will be established.

Examples:

	mdio {