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Commit bd9bc355 authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher
Browse files

drm/amd/display: Fix takover from VGA mode 



HW Engineer's Notes:
 During switch from vga->extended, if we set the VGA_TEST_ENABLE and then
 hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
 Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
 VGA_TEST_ENABLE, to leave it in the same state as before.

Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9fe8f03b

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h

+8 −2
Original line number Diff line number Diff line
@@ -236,6 +236,7 @@ 
	SR(D2VGA_CONTROL), \

	SR(D3VGA_CONTROL), \

	SR(D4VGA_CONTROL), \

	SR(VGA_TEST_CONTROL), \

	SR(DC_IP_REQUEST_CNTL), \

	BL_REG_LIST()
@@ -337,6 +338,7 @@ struct dce_hwseq_registers { 
	uint32_t D2VGA_CONTROL;

	uint32_t D3VGA_CONTROL;

	uint32_t D4VGA_CONTROL;

	uint32_t VGA_TEST_CONTROL;

	/* MMHUB registers. read only. temporary hack */

	uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;

	uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
@@ -494,7 +496,9 @@ struct dce_hwseq_registers { 
	HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \

	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)

	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh), \

	HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\

	HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)



#define HWSEQ_REG_FIELD_LIST(type) \

	type DCFE_CLOCK_ENABLE; \
@@ -583,7 +587,9 @@ struct dce_hwseq_registers { 
	type DCFCLK_GATE_DIS; \

	type DCHUBBUB_GLOBAL_TIMER_REFDIV; \

	type DENTIST_DPPCLK_WDIVIDER; \

	type DENTIST_DISPCLK_WDIVIDER;

	type DENTIST_DISPCLK_WDIVIDER; \

	type VGA_TEST_ENABLE; \

	type VGA_TEST_RENDER_START;



struct dce_hwseq_shift {

	HWSEQ_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+10 −0
Original line number Diff line number Diff line
@@ -242,6 +242,16 @@ static void disable_vga( 
	REG_WRITE(D2VGA_CONTROL, 0);

	REG_WRITE(D3VGA_CONTROL, 0);

	REG_WRITE(D4VGA_CONTROL, 0);



	/* HW Engineer's Notes:

	 *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and

	 *  then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.

	 *

	 *  Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset

	 *  VGA_TEST_ENABLE, to leave it in the same state as before.

	 */

	REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);

	REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);

}



static void dpp_pg_control(