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Commit bd1296a8 authored by Chetan C R's avatar Chetan C R
Browse files

ARM: dts: msm: Add rpmcc and gcc clock nodes for SDM439 

Add rpmcc, gcc clock controller support for
SDM429 and SDM439 targets.

Change-Id: I50a1312fbbce8952715c0cb9d9df35fdcada04a3
parent 8b44ccd7

qcom/msm8917.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -550,7 +550,7 @@ 
	};



	rpmcc: qcom,rpmcc {

		compatible = "qcom,rpmcc-msm8917";

		compatible = "qcom,rpmcc-qm215";

		#clock-cells = <1>;

	};

qcom/msm8937.dtsi

+3 −4
Original line number Diff line number Diff line
@@ -568,15 +568,14 @@ 
	};



	rpmcc: qcom,rpmcc {

		compatible = "qcom,rpmcc-msm8937";

		compatible = "qcom,rpmcc-sdm439";

		#clock-cells = <1>;

	};



	gcc: qcom,gcc@1800000 {

		compatible = "qcom,gcc-msm8937", "syscon";

		compatible = "qcom,gcc-sdm439", "syscon";

		reg = <0x1800000 0x80000>;

			 <0x00a6018 0x00004>;

		reg-names = "cc_base", "gpu-bin";

		reg-names = "cc_base";

		qcom,gcc_oxili_gfx3d_clk-opp-handle = <&msm_gpu>;

		vdd_cx-supply = <&pm8937_s2_level>;

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;

qcom/qm215.dtsi

+0 −4
Original line number Diff line number Diff line
@@ -23,10 +23,6 @@ 
	};

};



&rpmcc {

	compatible = "qcom,rpmcc-qm215";

};



&gcc {

	compatible = "qcom,gcc-qm215", "syscon";

};

qcom/sdm429.dtsi

+1 −7
Original line number Diff line number Diff line
@@ -105,13 +105,7 @@ 
};



&gcc {

	compatible = "qcom,gcc-sdm429";

	reg = <0x1800000 0x80000>,

		<0xb016000 0x00040>;

	reg-names = "cc_base", "apcs_c1_base";

	vdd_cx-supply = <&pm8953_s2_level>;

	vdd_hf_dig-supply = <&pm8953_s2_level_ao>;

	vdd_hf_pll-supply = <&pm8953_l7_ao>;

};



&debugcc {
@@ -218,7 +212,7 @@ 
};



&gcc_mdss {

	compatible = "qcom,gcc-mdss-sdm429";

	compatible = "qcom,gcc-mdss-sdm439";

	clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>,

		<&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>,

		<&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>,

qcom/sdm439.dtsi

+0 −11
Original line number Diff line number Diff line
@@ -324,18 +324,7 @@ 
};



&gcc {

	compatible = "qcom,gcc-sdm439";

	reg = <0x1800000 0x80000>,

		<0xb016000 0x00040>,

		<0xb116000 0x00040>,

		<0x00a6018 0x00004>;

	reg-names = "cc_base", "apcs_c1_base",

			"apcs_c0_base", "efuse";

	vdd_cx-supply = <&pm8953_s2_level>;

	vdd_sr2_dig-supply = <&pm8953_s2_level_ao>;

	vdd_sr2_pll-supply = <&pm8953_l7_ao>;

	vdd_hf_dig-supply = <&pm8953_s2_level_ao>;

	vdd_hf_pll-supply = <&pm8953_l7_ao>;

};



&gcc_mdss {