Merge "msm: camera: icp: setting QoS for a5 firmware" (bce2f4a7) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/media/platform/msm/camera/cam_icp/icp_hw/a5_hw/a5_core.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -241,6 +241,7 @@ int cam_a5_init_hw(void *device_priv,
		struct cam_hw_info *a5_dev = device_priv;
		struct cam_hw_soc_info *soc_info = NULL;
		struct cam_a5_device_core_info *core_info = NULL;
		struct a5_soc_info *a5_soc_info;
		struct cam_icp_cpas_vote cpas_vote;
		int rc = 0;

		@@ -258,6 +259,8 @@ int cam_a5_init_hw(void *device_priv,
		return -EINVAL;
		}

		a5_soc_info = soc_info->soc_private;

		cpas_vote.ahb_vote.type = CAM_VOTE_ABSOLUTE;
		cpas_vote.ahb_vote.vote.level = CAM_SVS_VOTE;
		cpas_vote.axi_vote.num_paths = 1;
		@@ -291,6 +294,12 @@ int cam_a5_init_hw(void *device_priv,
		CAM_ERR(CAM_ICP, "cpas stop is failed");
		else
		core_info->cpas_start = false;
		} else {
		CAM_DBG(CAM_ICP, "a5_qos %d", a5_soc_info->a5_qos_val);
		if (a5_soc_info->a5_qos_val)
		cam_io_w_mb(a5_soc_info->a5_qos_val,
		soc_info->reg_map[A5_SIERRA_BASE].mem_base +
		ICP_SIERRA_A5_CSR_ACCESS);
		}

		error:

+2 −0

Original line number	Diff line number	Diff line
		@@ -20,6 +20,8 @@
		#define A5_WDT_0 0x2
		#define A5_WDT_1 0x4

		#define ICP_SIERRA_A5_CSR_ACCESS 0x3C

		#define ELF_GUARD_PAGE (2 * 1024 * 1024)

		struct cam_a5_device_hw_info {

+7 −0

Original line number	Diff line number	Diff line
		@@ -40,6 +40,13 @@ static int cam_a5_get_dt_properties(struct cam_hw_soc_info *soc_info)
		goto end;
		}

		rc = of_property_read_u32(of_node, "qos-val",
		&a5_soc_info->a5_qos_val);
		if (rc < 0) {
		CAM_WARN(CAM_ICP, "QoS need not be set");
		a5_soc_info->a5_qos_val = 0;
		}

		ubwc_cfg_ext = &a5_soc_info->uconfig.ubwc_cfg_ext;
		num_ubwc_cfg = of_property_count_u32_elems(of_node,
		"ubwc-ipe-fetch-cfg");

+1 −0

Original line number	Diff line number	Diff line
		@@ -20,6 +20,7 @@ struct a5_ubwc_cfg_ext {
		struct a5_soc_info {
		char *fw_name;
		bool ubwc_config_ext;
		uint32_t a5_qos_val;
		union {
		uint32_t ubwc_cfg[ICP_UBWC_MAX];
		struct a5_ubwc_cfg_ext ubwc_cfg_ext;