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Commit bcc8d312 authored by Tony Lindgren's avatar Tony Lindgren
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Merge commit '20a2742e' into omap-for-v4.16/dt-clk

parents 80a06c0d 20a2742e

Documentation/devicetree/bindings/bus/ti-sysc.txt

+36 −0
Original line number Diff line number Diff line
@@ -26,6 +26,8 @@ Required standard properties: 
		or one of the following derivative types for hardware

		needing special workarounds:



		"ti,sysc-omap2-timer"

		"ti,sysc-omap4-timer"

		"ti,sysc-omap3430-sr"

		"ti,sysc-omap3630-sr"

		"ti,sysc-omap4-sr"
@@ -49,6 +51,26 @@ Required standard properties: 


Optional properties:



- ti,sysc-mask	shall contain mask of supported register bits for the

		SYSCONFIG register as documented in the Technical Reference

		Manual (TRM) for the interconnect target module



- ti,sysc-midle	list of master idle modes supported by the interconnect

		target module as documented in the TRM for SYSCONFIG

		register MIDLEMODE bits



- ti,sysc-sidle	list of slave idle modes supported by the interconnect

		target module as documented in the TRM for SYSCONFIG

		register SIDLEMODE bits



- ti,sysc-delay-us	delay needed after OCP softreset before accssing

			SYSCONFIG register again



- ti,syss-mask	optional mask of reset done status bits as described in the

		TRM for SYSSTATUS registers, typically 1 with some devices

		having separate reset done bits for children like OHCI and

		EHCI



- clocks	clock specifier for each name in the clock-names as

		specified in the binding documentation for ti-clkctrl,

		typically available for all interconnect targets on TI SoCs
@@ -61,6 +83,9 @@ Optional properties: 
- ti,hwmods	optional TI interconnect module name to use legacy

		hwmod platform data



- ti,no-reset-on-init	interconnect target module should not be reset at init



- ti,no-idle-on-init	interconnect target module should not be idled at init



Example: Single instance of MUSB controller on omap4 using interconnect ranges

using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
@@ -74,6 +99,17 @@ using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): 
		reg-names = "rev", "sysc", "syss";

		clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;

		clock-names = "fck";

		ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |

				 SYSC_OMAP2_SOFTRESET |

				 SYSC_OMAP2_AUTOIDLE)>;

		ti,sysc-midle = <SYSC_IDLE_FORCE>,

				<SYSC_IDLE_NO>,

				<SYSC_IDLE_SMART>;

		ti,sysc-sidle = <SYSC_IDLE_FORCE>,

				<SYSC_IDLE_NO>,

				<SYSC_IDLE_SMART>,

				<SYSC_IDLE_SMART_WKUP>;

		ti,syss-mask = <1>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0x2b000 0x1000>;

include/dt-bindings/bus/ti-sysc.h

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/* TI sysc interconnect target module defines */



/* Generic sysc found on omap2 and later, also known as type1 */

#define SYSC_OMAP2_CLOCKACTIVITY	(3 << 8)

#define SYSC_OMAP2_EMUFREE		(1 << 5)

#define SYSC_OMAP2_ENAWAKEUP		(1 << 2)

#define SYSC_OMAP2_SOFTRESET		(1 << 1)

#define SYSC_OMAP2_AUTOIDLE		(1 << 0)



/* Generic sysc found on omap4 and later, also known as type2 */

#define SYSC_OMAP4_DMADISABLE		(1 << 16)

#define SYSC_OMAP4_FREEEMU		(1 << 1)	/* Also known as EMUFREE */

#define SYSC_OMAP4_SOFTRESET		(1 << 0)



/* SmartReflex sysc found on 36xx and later */

#define SYSC_OMAP3_SR_ENAWAKEUP		(1 << 26)



/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */

#define SYSC_IDLE_FORCE			0

#define SYSC_IDLE_NO			1

#define SYSC_IDLE_SMART			2

#define SYSC_IDLE_SMART_WKUP		3