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Commit bca028e7 authored by Ben Dooks's avatar Ben Dooks
Browse files

ARM: mvebu: support running big-endian 



Add indication we can run these cores in BE mode, and ensure that the
secondary CPU is set to big-endian mode in the initialisation code as
the initial code runs little-endian.

Signed-off-by: default avatarBen Dooks <ben.dooks@codethink.co.uk>
Tested-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 50eec2fc

arch/arm/mach-mvebu/Kconfig

+1 −0
Original line number Diff line number Diff line 
config ARCH_MVEBU

	bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7

	select ARCH_SUPPORTS_BIG_ENDIAN

	select CLKSRC_MMIO

	select COMMON_CLK

	select GENERIC_CLOCKEVENTS

arch/arm/mach-mvebu/coherency_ll.S

+3 −0
Original line number Diff line number Diff line
@@ -20,6 +20,8 @@ 
#define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0

#define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4



#include <asm/assembler.h>



	.text

/*

 * r0: Coherency fabric base register address
@@ -29,6 +31,7 @@ ENTRY(ll_set_cpu_coherent) 
	/* Create bit by cpu index */

	mov	r3, #(1 << 24)

	lsl	r1, r3, r1

ARM_BE8(rev	r1, r1)



	/* Add CPU to SMP group - Atomic */

	add	r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET

arch/arm/mach-mvebu/headsmp.S

+4 −0
Original line number Diff line number Diff line
@@ -21,12 +21,16 @@ 
#include <linux/linkage.h>

#include <linux/init.h>



#include <asm/assembler.h>



/*

 * Armada XP specific entry point for secondary CPUs.

 * We add the CPU to the coherency fabric and then jump to secondary

 * startup

 */

ENTRY(armada_xp_secondary_startup)

 ARM_BE8(setend	be )			@ go BE8 if entered LE



	/* Get coherency fabric base physical address */

	adr	r0, 1f

	ldr	r1, [r0]