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Commit bbde630b authored by Kumar Gala's avatar Kumar Gala Committed by Linus Torvalds
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[PATCH] ppc32: Added cputable entry for 7448 



Added cputable entry for 7448 as well adding it to checks for saving and
restoring of cpu state.

Signed-off-by: default avatarKumar Gala <kumar.gala@freescale.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent e8834801

arch/ppc/kernel/cpu_setup_6xx.S

+4 −0
Original line number Diff line number Diff line
@@ -327,6 +327,7 @@ _GLOBAL(__save_cpu_setup) 
	cmplwi	cr4,r3,0x8002	/* 7457 */

	cmplwi	cr5,r3,0x8003	/* 7447A */

	cmplwi	cr6,r3,0x7000	/* 750FX */

	cmplwi	cr7,r3,0x8004	/* 7448 */

	/* cr1 is 7400 || 7410 */

	cror	4*cr1+eq,4*cr1+eq,4*cr2+eq

	/* cr0 is 74xx */
@@ -334,6 +335,7 @@ _GLOBAL(__save_cpu_setup) 
	cror	4*cr0+eq,4*cr0+eq,4*cr4+eq

	cror	4*cr0+eq,4*cr0+eq,4*cr1+eq

	cror	4*cr0+eq,4*cr0+eq,4*cr5+eq

	cror	4*cr0+eq,4*cr0+eq,4*cr7+eq

	bne	1f

	/* Backup 74xx specific regs */

	mfspr	r4,SPRN_MSSCR0
@@ -396,6 +398,7 @@ _GLOBAL(__restore_cpu_setup) 
	cmplwi	cr4,r3,0x8002	/* 7457 */

	cmplwi	cr5,r3,0x8003	/* 7447A */

	cmplwi	cr6,r3,0x7000	/* 750FX */

	cmplwi	cr7,r3,0x8004	/* 7448 */

	/* cr1 is 7400 || 7410 */

	cror	4*cr1+eq,4*cr1+eq,4*cr2+eq

	/* cr0 is 74xx */
@@ -403,6 +406,7 @@ _GLOBAL(__restore_cpu_setup) 
	cror	4*cr0+eq,4*cr0+eq,4*cr4+eq

	cror	4*cr0+eq,4*cr0+eq,4*cr1+eq

	cror	4*cr0+eq,4*cr0+eq,4*cr5+eq

	cror	4*cr0+eq,4*cr0+eq,4*cr7+eq

	bne	2f

	/* Restore 74xx specific regs */

	lwz	r4,CS_MSSCR0(r5)

arch/ppc/kernel/cputable.c

+16 −0
Original line number Diff line number Diff line
@@ -550,6 +550,22 @@ struct cpu_spec cpu_specs[] = { 
		.num_pmcs		= 6,

		.cpu_setup		= __setup_cpu_745x

	},

	{	/* 7448 */

		.pvr_mask		= 0xffff0000,

		.pvr_value		= 0x80040000,

		.cpu_name		= "7448",

		.cpu_features		= CPU_FTR_COMMON |

			CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |

			CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |

			CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |

			CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |

			CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,

		.cpu_user_features	= COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,

		.icache_bsize		= 32,

		.dcache_bsize		= 32,

		.num_pmcs		= 6,

		.cpu_setup		= __setup_cpu_745x

	},

	{	/* 82xx (8240, 8245, 8260 are all 603e cores) */

		.pvr_mask		= 0x7fff0000,

		.pvr_value		= 0x00810000,