Loading include/asm-mips/byteorder.h +18 −0 Original line number Diff line number Diff line Loading @@ -39,6 +39,24 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) } #define __arch__swab32(x) ___arch__swab32(x) #ifdef CONFIG_CPU_MIPS64_R2 static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) { __asm__( " dsbh %0, %1 \n" " dshd %0, %0 \n" " drotr %0, %0, 32 \n" : "=r" (x) : "r" (x)); return x; } #define __arch__swab64(x) ___arch__swab64(x) #endif /* CONFIG_CPU_MIPS64_R2 */ #endif /* CONFIG_CPU_MIPSR2 */ #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) Loading Loading
include/asm-mips/byteorder.h +18 −0 Original line number Diff line number Diff line Loading @@ -39,6 +39,24 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) } #define __arch__swab32(x) ___arch__swab32(x) #ifdef CONFIG_CPU_MIPS64_R2 static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) { __asm__( " dsbh %0, %1 \n" " dshd %0, %0 \n" " drotr %0, %0, 32 \n" : "=r" (x) : "r" (x)); return x; } #define __arch__swab64(x) ___arch__swab64(x) #endif /* CONFIG_CPU_MIPS64_R2 */ #endif /* CONFIG_CPU_MIPSR2 */ #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) Loading