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Commit bb5368aa authored by Feifei Xu's avatar Feifei Xu Committed by Alex Deucher
Browse files

drm/amdgpu/gfx9: Add vega20 golden settings (v3) 



v2: squash in updates (Alex)
v3: squash in more updates (Alex)

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 940328fe

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+22 −0
Original line number Diff line number Diff line
@@ -108,6 +108,20 @@ static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800)

};



static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =

{

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000)

};



static const struct soc15_reg_golden golden_settings_gc_9_1[] =

{

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
@@ -241,6 +255,14 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 
						golden_settings_gc_9_2_1_vg12,

						ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));

		break;

	case CHIP_VEGA20:

		soc15_program_register_sequence(adev,

						golden_settings_gc_9_0,

						ARRAY_SIZE(golden_settings_gc_9_0));

		soc15_program_register_sequence(adev,

						golden_settings_gc_9_0_vg20,

						ARRAY_SIZE(golden_settings_gc_9_0_vg20));

		break;

	case CHIP_RAVEN:

		soc15_program_register_sequence(adev,

						 golden_settings_gc_9_1,