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Commit bac842da authored by Emmanuel Grumbach's avatar Emmanuel Grumbach
Browse files

iwlwifi: pcie: aggregate Flow Handler configuration writes 



Instead of waking up the device each time we write a
register, wake it up once, and writes the registers
at once.

Signed-off-by: default avatarEmmanuel Grumbach <emmanuel.grumbach@intel.com>
parent 5a51c03f

drivers/net/wireless/intel/iwlwifi/pcie/trans.c

+28 −28
Original line number Diff line number Diff line
@@ -616,39 +616,39 @@ static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, 
				   dma_addr_t phy_addr, u32 byte_cnt)

{

	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	unsigned long flags;

	int ret;



	trans_pcie->ucode_write_complete = false;



	iwl_write_direct32(trans,

			   FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),

	if (!iwl_trans_grab_nic_access(trans, &flags))

		return -EIO;



	iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),

		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);



	iwl_write_direct32(trans,

			   FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),

	iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),

		    dst_addr);



	iwl_write_direct32(trans,

			   FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),

	iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),

		    phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);



	iwl_write_direct32(trans,

			   FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),

	iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),

		    (iwl_get_dma_hi_addr(phy_addr)

			<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);



	iwl_write_direct32(trans,

			   FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),

			   1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |

			   1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |

	iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),

		    BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |

		    BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |

		    FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);



	iwl_write_direct32(trans,

			   FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),

	iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),

		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |

		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |

		    FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);



	iwl_trans_release_nic_access(trans, &flags);



	ret = wait_event_timeout(trans_pcie->ucode_write_waitq,

				 trans_pcie->ucode_write_complete, 5 * HZ);

	if (!ret) {