Merge remote-tracking branches 'spi/topic/pl022', 'spi/topic/pxa2xx',...

			 "renesas,sh-mobile-msiof" for SH Mobile series.

			 Examples with soctypes are:

			 "renesas,msiof-r8a7790" (R-Car H2)

			 "renesas,msiof-r8a7791" (R-Car M2)

- reg                  : Offset and length of the register set for the device

			 "renesas,msiof-r8a7791" (R-Car M2-W)

			 "renesas,msiof-r8a7792" (R-Car V2H)

			 "renesas,msiof-r8a7793" (R-Car M2-N)

			 "renesas,msiof-r8a7794" (R-Car E2)

- reg                  : A list of offsets and lengths of the register sets for

			 the device.

			 If only one register set is present, it is to be used

			 by both the CPU and the DMA engine.

			 If two register sets are present, the first is to be

			 used by the CPU, and the second is to be used by the

			 DMA engine.

- interrupt-parent     : The phandle for the interrupt controller that

			 services interrupts for this device

- interrupts           : Interrupt specifier

Optional properties:

- clocks               : Must contain a reference to the functional clock.

- num-cs               : Total number of chip-selects (default is 1)

- dmas                 : Must contain a list of two references to DMA

			 specifiers, one for transmission, and one for

			 reception.

- dma-names            : Must contain a list of two DMA names, "tx" and "rx".

Optional properties, deprecated for soctype-specific bindings:

- renesas,tx-fifo-size : Overrides the default tx fifo size given in words

			 (default is 64)

- renesas,rx-fifo-size : Overrides the default rx fifo size given in words

			 (default is 64, or 256 on R-Car H2 and M2)

			 (default is 64, or 256 on R-Car Gen2)

Pinctrl properties might be needed, too.  See

Documentation/devicetree/bindings/pinctrl/renesas,*.

	msiof0: spi@e6e20000 {

		compatible = "renesas,msiof-r8a7791";

		reg = <0 0xe6e20000 0 0x0064>;

		reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;

		interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;

		dmas = <&dmac0 0x51>, <&dmac0 0x52>;

		dma-names = "tx", "rx";

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

		        - "renesas,rspi-sh7757" (SH)

			- "renesas,rspi-r7s72100" (RZ/A1H)

			- "renesas,qspi-r8a7790" (R-Car H2)

			- "renesas,qspi-r8a7791" (R-Car M2)

			- "renesas,qspi-r8a7791" (R-Car M2-W)

			- "renesas,qspi-r8a7792" (R-Car V2H)

			- "renesas,qspi-r8a7793" (R-Car M2-N)

			- "renesas,qspi-r8a7794" (R-Car E2)

- reg              : Address start and address range size of the device

- interrupts       : A list of interrupt-specifiers, one for each entry in

		     interrupt-names.

Optional properties:

- clocks           : Must contain a reference to the functional clock.

- dmas             : Must contain a list of two references to DMA specifiers,

		     one for transmission, and one for reception.

- dma-names        : Must contain a list of two DMA names, "tx" and "rx".

Pinctrl properties might be needed, too.  See

Documentation/devicetree/bindings/pinctrl/renesas,*.

		num-cs = <1>;

		#address-cells = <1>;

		#size-cells = <0>;

		dmas = <&dmac0 0x17>, <&dmac0 0x18>;

		dma-names = "tx", "rx";

	};

	  additional documentation can be found a Documentation/spi/pxa2xx.

config SPI_PXA2XX_PCI

	def_tristate SPI_PXA2XX && PCI

	def_tristate SPI_PXA2XX && PCI && COMMON_CLK

config SPI_ROCKCHIP

	tristate "Rockchip SPI controller driver"

#define SSP_MIS(r)	(r + 0x01C)

#define SSP_ICR(r)	(r + 0x020)

#define SSP_DMACR(r)	(r + 0x024)

#define SSP_CSR(r)	(r + 0x030) /* vendor extension */

#define SSP_ITCR(r)	(r + 0x080)

#define SSP_ITIP(r)	(r + 0x084)

#define SSP_ITOP(r)	(r + 0x088)

/* Transmit DMA Enable bit */

#define SSP_DMACR_MASK_TXDMAE		(0x1UL << 1)

/*

 * SSP Chip Select Control Register - SSP_CSR

 * (vendor extension)

 */

#define SSP_CSR_CSVALUE_MASK		(0x1FUL << 0)

/*

 * SSP Integration Test control Register - SSP_ITCR

 */

 * @extended_cr: 32 bit wide control register 0 with extra

 * features and extra features in CR1 as found in the ST variants

 * @pl023: supports a subset of the ST extensions called "PL023"

 * @internal_cs_ctrl: supports chip select control register

 */

struct vendor_data {

	int fifodepth;

	bool extended_cr;

	bool pl023;

	bool loopback;

	bool internal_cs_ctrl;

};

/**

	pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);

}

/**

 * internal_cs_control - Control chip select signals via SSP_CSR.

 * @pl022: SSP driver private data structure

 * @command: select/delect the chip

 *

 * Used on controller with internal chip select control via SSP_CSR register

 * (vendor extension). Each of the 5 LSB in the register controls one chip

 * select signal.

 */

static void internal_cs_control(struct pl022 *pl022, u32 command)

{

	u32 tmp;

	tmp = readw(SSP_CSR(pl022->virtbase));

	if (command == SSP_CHIP_SELECT)

		tmp &= ~BIT(pl022->cur_cs);

	else

		tmp |= BIT(pl022->cur_cs);

	writew(tmp, SSP_CSR(pl022->virtbase));

}

static void pl022_cs_control(struct pl022 *pl022, u32 command)

{

	if (gpio_is_valid(pl022->cur_cs))

	if (pl022->vendor->internal_cs_ctrl)

		internal_cs_control(pl022, command);

	else if (gpio_is_valid(pl022->cur_cs))

		gpio_set_value(pl022->cur_cs, command);

	else

		pl022->cur_chip->cs_control(command);

	pl022->vendor = id->data;

	pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int),

					  GFP_KERNEL);

	if (!pl022->chipselects) {

		status = -ENOMEM;

		goto err_no_mem;

	}

	/*

	 * Bus Number Which has been Assigned to this SSP controller

	if (platform_info->num_chipselect && platform_info->chipselects) {

		for (i = 0; i < num_cs; i++)

			pl022->chipselects[i] = platform_info->chipselects[i];

	} else if (pl022->vendor->internal_cs_ctrl) {

		for (i = 0; i < num_cs; i++)

			pl022->chipselects[i] = i;

	} else if (IS_ENABLED(CONFIG_OF)) {

		for (i = 0; i < num_cs; i++) {

			int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);

	amba_release_regions(adev);

 err_no_ioregion:

 err_no_gpio:

 err_no_mem:

	spi_master_put(master);

	return status;

}

	.extended_cr = false,

	.pl023 = false,

	.loopback = true,

	.internal_cs_ctrl = false,

};

static struct vendor_data vendor_st = {

	.extended_cr = true,

	.pl023 = false,

	.loopback = true,

	.internal_cs_ctrl = false,

};

static struct vendor_data vendor_st_pl023 = {

	.extended_cr = true,

	.pl023 = true,

	.loopback = false,

	.internal_cs_ctrl = false,

};

static struct vendor_data vendor_lsi = {

	.fifodepth = 8,

	.max_bpw = 16,

	.unidir = false,

	.extended_cr = false,

	.pl023 = false,

	.loopback = true,

	.internal_cs_ctrl = true,

};

static struct amba_id pl022_ids[] = {

		.mask	= 0xffffffff,

		.data	= &vendor_st_pl023,

	},

	{

		/*

		 * PL022 variant that has a chip select control register whih

		 * allows control of 5 output signals nCS[0:4].

		 */

		.id	= 0x000b6022,

		.mask	= 0x000fffff,

		.data	= &vendor_lsi,

	},

	{ 0, 0 },

};

#include <linux/of_device.h>

#include <linux/module.h>

#include <linux/spi/pxa2xx_spi.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

enum {

	PORT_CE4100,

	int tx_chan_id;

	int rx_slave_id;

	int rx_chan_id;

	unsigned long max_clk_rate;

};

static struct pxa_spi_info spi_info_configs[] = {

		.tx_chan_id = -1,

		.rx_slave_id = -1,

		.rx_chan_id = -1,

		.max_clk_rate = 3686400,

	},

	[PORT_BYT] = {

		.type = LPSS_SSP,

		.tx_chan_id = 0,

		.rx_slave_id = 1,

		.rx_chan_id = 1,

		.max_clk_rate = 50000000,

	},

};

	struct pxa2xx_spi_master spi_pdata;

	struct ssp_device *ssp;

	struct pxa_spi_info *c;

	char buf[40];

	ret = pcim_enable_device(dev);

	if (ret)

	ssp->port_id = (c->port_id >= 0) ? c->port_id : dev->devfn;

	ssp->type = c->type;

	snprintf(buf, sizeof(buf), "pxa2xx-spi.%d", ssp->port_id);

	ssp->clk = clk_register_fixed_rate(&dev->dev, buf , NULL,

					CLK_IS_ROOT, c->max_clk_rate);

	 if (IS_ERR(ssp->clk))

		return PTR_ERR(ssp->clk);

	memset(&pi, 0, sizeof(pi));

	pi.parent = &dev->dev;

	pi.name = "pxa2xx-spi";

	pi.size_data = sizeof(spi_pdata);

	pdev = platform_device_register_full(&pi);

	if (IS_ERR(pdev))

	if (IS_ERR(pdev)) {

		clk_unregister(ssp->clk);

		return PTR_ERR(pdev);

	}

	pci_set_drvdata(dev, pdev);

static void pxa2xx_spi_pci_remove(struct pci_dev *dev)

{

	struct platform_device *pdev = pci_get_drvdata(dev);

	struct pxa2xx_spi_master *spi_pdata;

	spi_pdata = dev_get_platdata(&pdev->dev);

	platform_device_unregister(pdev);

	clk_unregister(spi_pdata->ssp.clk);

}

static const struct pci_device_id pxa2xx_spi_pci_devices[] = {