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Commit ba8a21cf authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amdgpu/smu9: update to latest driver interface 



Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 40f06773

drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h

+53 −4
Original line number Diff line number Diff line
@@ -30,7 +30,9 @@ 
 * SMU TEAM: Always increment the interface version if

 * any structure is changed in this file

 */

#define SMU9_DRIVER_IF_VERSION 0xa

#define SMU9_DRIVER_IF_VERSION 0xB



#define PPTABLE_V10_SMU_VERSION 1



#define NUM_GFXCLK_DPM_LEVELS  8

#define NUM_UVD_DPM_LEVELS     8
@@ -87,6 +89,11 @@ typedef struct { 
  int32_t a0;

  int32_t a1;

  int32_t a2;



  uint8_t a0_shift;

  uint8_t a1_shift;

  uint8_t a2_shift;

  uint8_t padding;

} GbVdroopTable_t;



typedef struct {
@@ -293,7 +300,9 @@ typedef struct { 
  uint16_t     Platform_sigma;

  uint16_t     PSM_Age_CompFactor;



  uint32_t     Reserved[20];

  uint32_t     DpmLevelPowerDelta;



  uint32_t     Reserved[19];



  /* Padding - ignore */

  uint32_t     MmHubPadding[7]; /* SMU internal use */
@@ -350,8 +359,8 @@ typedef struct { 
typedef struct {

  uint16_t avgPsmCount[30];

  uint16_t minPsmCount[30];

  uint16_t avgPsmVoltage[30]; /* in mV with 2 fractional bits */

  uint16_t minPsmVoltage[30]; /* in mV with 2 fractional bits */

  float    avgPsmVoltage[30];

  float    minPsmVoltage[30];



  uint32_t MmHubPadding[7]; /* SMU internal use */

} AvfsDebugTable_t;
@@ -414,5 +423,45 @@ typedef struct { 
#define UCLK_SWITCH_SLOW 0

#define UCLK_SWITCH_FAST 1



/* GFX DIDT Configuration */

#define SQ_Enable_MASK 0x1

#define SQ_IR_MASK 0x2

#define SQ_PCC_MASK 0x4

#define SQ_EDC_MASK 0x8



#define TCP_Enable_MASK 0x100

#define TCP_IR_MASK 0x200

#define TCP_PCC_MASK 0x400

#define TCP_EDC_MASK 0x800



#define TD_Enable_MASK 0x10000

#define TD_IR_MASK 0x20000

#define TD_PCC_MASK 0x40000

#define TD_EDC_MASK 0x80000



#define DB_Enable_MASK 0x1000000

#define DB_IR_MASK 0x2000000

#define DB_PCC_MASK 0x4000000

#define DB_EDC_MASK 0x8000000



#define SQ_Enable_SHIFT 0

#define SQ_IR_SHIFT 1

#define SQ_PCC_SHIFT 2

#define SQ_EDC_SHIFT 3



#define TCP_Enable_SHIFT 8

#define TCP_IR_SHIFT 9

#define TCP_PCC_SHIFT 10

#define TCP_EDC_SHIFT 11



#define TD_Enable_SHIFT 16

#define TD_IR_SHIFT 17

#define TD_PCC_SHIFT 18

#define TD_EDC_SHIFT 19



#define DB_Enable_SHIFT 24

#define DB_IR_SHIFT 25

#define DB_PCC_SHIFT 26

#define DB_EDC_SHIFT 27



#endif