Commit b9ec866d authored Jan 06, 2017 by Patrice Chotard

ARM: dts: STiH410-family: fix wrong parent clock frequency



The clock parent was lower than child clock which is not correct.
In some use case, it leads to division by zero.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>

parent b005ebf9

arch/arm/boot/dts/stih410.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -131,7 +131,7 @@
		<&clk_s_d2_quadfs 0>;

		assigned-clock-rates = <297000000>,
		<108000000>,
		<297000000>,
		<0>,
		<400000000>,
		<400000000>;