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Commit b9934878 authored by Flora Cui's avatar Flora Cui Committed by Alex Deucher
Browse files

drm/amdgpu: update Polaris11 golden setting 



Signed-off-by: default avatarFlora Cui <Flora.Cui@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 35621b80

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -137,7 +137,7 @@ static const u32 polaris11_golden_settings_a11[] = 
	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,

	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,

	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,

	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,

	mmFBC_DEBUG1, 0xffffffff, 0x00000008,

	mmFBC_DEBUG1, 0xffffffff, 0x00000008,

	mmFBC_MISC, 0x9f313fff, 0x14300008,

	mmFBC_MISC, 0x9f313fff, 0x14302008,

	mmHDMI_CONTROL, 0x313f031f, 0x00000011,

	mmHDMI_CONTROL, 0x313f031f, 0x00000011,

};

};

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+3 −2
Original line number Original line Diff line number Diff line
@@ -267,10 +267,13 @@ static const u32 tonga_mgcg_cgcg_init[] = 




static const u32 golden_settings_polaris11_a11[] =

static const u32 golden_settings_polaris11_a11[] =

{

{

	mmCB_HW_CONTROL, 0xfffdf3cf, 0x00006208,

	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,

	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,

	mmDB_DEBUG2, 0xf00fffff, 0x00000400,

	mmDB_DEBUG2, 0xf00fffff, 0x00000400,

	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,

	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,

	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,

	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,

	mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,

	mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,

	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,

	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,

	mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,

	mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,

	mmSQ_CONFIG, 0x07f80000, 0x07180000,

	mmSQ_CONFIG, 0x07f80000, 0x07180000,
@@ -284,8 +287,6 @@ static const u32 golden_settings_polaris11_a11[] = 
static const u32 polaris11_golden_common_all[] =

static const u32 polaris11_golden_common_all[] =

{

{

	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,

	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,

	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,

	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,

	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,

	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,

	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,

	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,

	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,

	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -109,10 +109,12 @@ static const u32 fiji_mgcg_cgcg_init[] = 
static const u32 golden_settings_polaris11_a11[] =

static const u32 golden_settings_polaris11_a11[] =

{

{

	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,

	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,

	mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,

	mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,

	mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,

	mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,

	mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,

	mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,

	mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,

	mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,

	mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,

	mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,

	mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,

	mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,

	mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,

	mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,

	mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,

	mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,