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Commit b97872d4 authored by Viresh Kumar's avatar Viresh Kumar Committed by Shawn Guo
Browse files

ARM: dts: imx: Add missing OPP properties for CPUs 



The OPP properties, like "operating-points", should either be present
for all the CPUs of a cluster or none. If these are present only for a
subset of CPUs of a cluster then things will start falling apart as soon
as the CPUs are brought online in a different order. For example, this
will happen because the operating system looks for such properties in
the CPU node it is trying to bring up, so that it can create an OPP
table.

Add such missing properties.

Fix other missing properties (like clocks, supply, clock latency) as
well to make it all work.

Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 77cf8a00

arch/arm/boot/dts/imx6dl.dtsi

+23 −0
Original line number Diff line number Diff line
@@ -51,6 +51,29 @@ 
			device_type = "cpu";

			reg = <1>;

			next-level-cache = <&L2>;

			operating-points = <

				/* kHz    uV */

				996000  1250000

				792000  1175000

				396000  1150000

			>;

			fsl,soc-operating-points = <

				/* ARM kHz  SOC-PU uV */

				996000	1175000

				792000	1175000

				396000	1175000

			>;

			clock-latency = <61036>; /* two CLK32 periods */

			clocks = <&clks IMX6QDL_CLK_ARM>,

				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,

				 <&clks IMX6QDL_CLK_STEP>,

				 <&clks IMX6QDL_CLK_PLL1_SW>,

				 <&clks IMX6QDL_CLK_PLL1_SYS>;

			clock-names = "arm", "pll2_pfd2_396m", "step",

				      "pll1_sw", "pll1_sys";

			arm-supply = <&reg_arm>;

			pu-supply = <&reg_pu>;

			soc-supply = <&reg_soc>;

		};

	};

arch/arm/boot/dts/imx6q-cm-fx6.dts

+66 −0
Original line number Diff line number Diff line
@@ -187,6 +187,72 @@ 
	>;

};



&cpu1 {

	/*

	 * Although the imx6q fuse indicates that 1.2GHz operation is possible,

	 * the module behaves unstable at this frequency. Hence, remove the

	 * 1.2GHz operation point here.

	 */

	operating-points = <

		/* kHz	uV */

		996000	1250000

		852000	1250000

		792000	1175000

		396000	975000

	>;

	fsl,soc-operating-points = <

		/* ARM kHz	SOC-PU uV */

		996000		1250000

		852000		1250000

		792000		1175000

		396000		1175000

	>;

};



&cpu2 {

	/*

	 * Although the imx6q fuse indicates that 1.2GHz operation is possible,

	 * the module behaves unstable at this frequency. Hence, remove the

	 * 1.2GHz operation point here.

	 */

	operating-points = <

		/* kHz	uV */

		996000	1250000

		852000	1250000

		792000	1175000

		396000	975000

	>;

	fsl,soc-operating-points = <

		/* ARM kHz	SOC-PU uV */

		996000		1250000

		852000		1250000

		792000		1175000

		396000		1175000

	>;

};



&cpu3 {

	/*

	 * Although the imx6q fuse indicates that 1.2GHz operation is possible,

	 * the module behaves unstable at this frequency. Hence, remove the

	 * 1.2GHz operation point here.

	 */

	operating-points = <

		/* kHz	uV */

		996000	1250000

		852000	1250000

		792000	1175000

		396000	975000

	>;

	fsl,soc-operating-points = <

		/* ARM kHz	SOC-PU uV */

		996000		1250000

		852000		1250000

		792000		1175000

		396000		1175000

	>;

};



&ecspi1 {

	cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>;

	pinctrl-names = "default";

arch/arm/boot/dts/imx6q.dtsi

+84 −3
Original line number Diff line number Diff line
@@ -51,25 +51,106 @@ 
			soc-supply = <&reg_soc>;

		};



		cpu@1 {

		cpu1: cpu@1 {

			compatible = "arm,cortex-a9";

			device_type = "cpu";

			reg = <1>;

			next-level-cache = <&L2>;

			operating-points = <

				/* kHz    uV */

				1200000 1275000

				996000  1250000

				852000  1250000

				792000  1175000

				396000  975000

			>;

			fsl,soc-operating-points = <

				/* ARM kHz  SOC-PU uV */

				1200000 1275000

				996000	1250000

				852000	1250000

				792000	1175000

				396000	1175000

			>;

			clock-latency = <61036>; /* two CLK32 periods */

			clocks = <&clks IMX6QDL_CLK_ARM>,

				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,

				 <&clks IMX6QDL_CLK_STEP>,

				 <&clks IMX6QDL_CLK_PLL1_SW>,

				 <&clks IMX6QDL_CLK_PLL1_SYS>;

			clock-names = "arm", "pll2_pfd2_396m", "step",

				      "pll1_sw", "pll1_sys";

			arm-supply = <&reg_arm>;

			pu-supply = <&reg_pu>;

			soc-supply = <&reg_soc>;

		};



		cpu@2 {

		cpu2: cpu@2 {

			compatible = "arm,cortex-a9";

			device_type = "cpu";

			reg = <2>;

			next-level-cache = <&L2>;

			operating-points = <

				/* kHz    uV */

				1200000 1275000

				996000  1250000

				852000  1250000

				792000  1175000

				396000  975000

			>;

			fsl,soc-operating-points = <

				/* ARM kHz  SOC-PU uV */

				1200000 1275000

				996000	1250000

				852000	1250000

				792000	1175000

				396000	1175000

			>;

			clock-latency = <61036>; /* two CLK32 periods */

			clocks = <&clks IMX6QDL_CLK_ARM>,

				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,

				 <&clks IMX6QDL_CLK_STEP>,

				 <&clks IMX6QDL_CLK_PLL1_SW>,

				 <&clks IMX6QDL_CLK_PLL1_SYS>;

			clock-names = "arm", "pll2_pfd2_396m", "step",

				      "pll1_sw", "pll1_sys";

			arm-supply = <&reg_arm>;

			pu-supply = <&reg_pu>;

			soc-supply = <&reg_soc>;

		};



		cpu@3 {

		cpu3: cpu@3 {

			compatible = "arm,cortex-a9";

			device_type = "cpu";

			reg = <3>;

			next-level-cache = <&L2>;

			operating-points = <

				/* kHz    uV */

				1200000 1275000

				996000  1250000

				852000  1250000

				792000  1175000

				396000  975000

			>;

			fsl,soc-operating-points = <

				/* ARM kHz  SOC-PU uV */

				1200000 1275000

				996000	1250000

				852000	1250000

				792000	1175000

				396000	1175000

			>;

			clock-latency = <61036>; /* two CLK32 periods */

			clocks = <&clks IMX6QDL_CLK_ARM>,

				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,

				 <&clks IMX6QDL_CLK_STEP>,

				 <&clks IMX6QDL_CLK_PLL1_SW>,

				 <&clks IMX6QDL_CLK_PLL1_SYS>;

			clock-names = "arm", "pll2_pfd2_396m", "step",

				      "pll1_sw", "pll1_sys";

			arm-supply = <&reg_arm>;

			pu-supply = <&reg_pu>;

			soc-supply = <&reg_soc>;

		};

	};

arch/arm/boot/dts/imx7d.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -18,6 +18,11 @@ 
			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <1>;

			operating-points = <

				/* KHz	uV */

				996000	1075000

				792000	975000

			>;

			clock-frequency = <996000000>;

			operating-points-v2 = <&cpu0_opp_table>;

		};