clk: qcom: gpucc-scuba: Add support for GPUCC clock driver (b90d9c99) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/clk/qcom/Kconfig

+9 −0

Original line number	Diff line number	Diff line
		@@ -524,3 +524,12 @@ config QM_DISPCC_SCUBA
		SCUBA devices.
		Say Y if you want to support display devices and functionality such as
		splash screen.

		config QM_GPUCC_SCUBA
		tristate "SCUBA Graphics Clock Controller"
		select QM_GCC_SCUBA
		help
		Support for the graphics clock controller on Qualcomm Technologies, Inc.
		SCUBA devices.
		Say Y if you want to support graphics controller devices
		and it's functionalities.

drivers/clk/qcom/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -51,6 +51,7 @@ obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
		obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
		obj-$(CONFIG_QM_DISPCC_SCUBA) += dispcc-scuba.o
		obj-$(CONFIG_QM_GCC_SCUBA) += gcc-scuba.o
		obj-$(CONFIG_QM_GPUCC_SCUBA) += gpucc-scuba.o
		obj-$(CONFIG_SDM_CAMCC_LAGOON) += camcc-lagoon.o
		obj-$(CONFIG_SDM_DEBUGCC_LAGOON) += debugcc-lagoon.o
		obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o

drivers/clk/qcom/gpucc-scuba.c

0 → 100644

+429 −0

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2020, The Linux Foundation. All rights reserved.
		*/

		#include <linux/clk.h>
		#include <linux/clk-provider.h>
		#include <linux/err.h>
		#include <linux/kernel.h>
		#include <linux/module.h>
		#include <linux/of_device.h>
		#include <linux/of.h>
		#include <linux/regmap.h>

		#include <dt-bindings/clock/qcom,gpucc-scuba.h>

		#include "clk-alpha-pll.h"
		#include "clk-branch.h"
		#include "clk-pll.h"
		#include "clk-rcg.h"
		#include "clk-regmap.h"
		#include "clk-regmap-divider.h"
		#include "clk-regmap-mux.h"
		#include "common.h"
		#include "reset.h"
		#include "vdd-level.h"

		static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);

		enum {
		P_BI_TCXO,
		P_CORE_BI_PLL_TEST_SE,
		P_GPLL0_OUT_MAIN,
		P_GPLL0_OUT_MAIN_DIV,
		P_GPU_CC_PLL0_2X_DIV_CLK_SRC,
		P_GPU_CC_PLL0_OUT_AUX,
		P_GPU_CC_PLL0_OUT_AUX2,
		P_GPU_CC_PLL0_OUT_MAIN,
		};

		static const struct parent_map gpu_cc_parent_map_0[] = {
		{ P_BI_TCXO, 0 },
		{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
		{ P_GPLL0_OUT_MAIN, 5 },
		{ P_GPLL0_OUT_MAIN_DIV, 6 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const gpu_cc_parent_names_0[] = {
		"bi_tcxo",
		"gpu_cc_pll0",
		"gpll0",
		"gpll0_out_main_div",
		"core_bi_pll_test_se",
		};

		static const struct parent_map gpu_cc_parent_map_1[] = {
		{ P_BI_TCXO, 0 },
		{ P_GPU_CC_PLL0_2X_DIV_CLK_SRC, 1 },
		{ P_GPU_CC_PLL0_OUT_AUX2, 2 },
		{ P_GPU_CC_PLL0_OUT_AUX, 3 },
		{ P_GPLL0_OUT_MAIN, 5 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const gpu_cc_parent_names_1[] = {
		"bi_tcxo",
		"gpu_cc_pll0",
		"gpu_cc_pll0",
		"gpu_cc_pll0",
		"gpll0",
		"core_bi_pll_test_se",
		};

		static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = {
		[CLK_ALPHA_PLL_TYPE_HUAYRA] = {
		[PLL_OFF_L_VAL] = 0x04,
		[PLL_OFF_ALPHA_VAL] = 0x08,
		[PLL_OFF_USER_CTL] = 0x0c,
		[PLL_OFF_CONFIG_CTL] = 0x10,
		[PLL_OFF_CONFIG_CTL_U] = 0x14,
		[PLL_OFF_CONFIG_CTL_U1] = 0x18,
		[PLL_OFF_TEST_CTL] = 0x1c,
		[PLL_OFF_TEST_CTL_U] = 0x20,
		[PLL_OFF_TEST_CTL_U1] = 0x24,
		[PLL_OFF_OPMODE] = 0x28,
		[PLL_OFF_STATUS] = 0x38,
		},
		};

		static const struct alpha_pll_config gpu_cc_pll0_config = {
		.l = 0x25,
		.config_ctl_val = 0x200D4828,
		.config_ctl_hi_val = 0x6,
		.test_ctl_val = 0x1C000000,
		.test_ctl_hi_val = 0x00004000,
		.user_ctl_val = 0xF,
		};

		static struct clk_alpha_pll gpu_cc_pll0 = {
		.offset = 0x0,
		.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_HUAYRA],
		.clkr = {
		.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_pll0",
		.parent_names = (const char *[]){ "bi_tcxo" },
		.num_parents = 1,
		.ops = &clk_alpha_pll_huayra_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 1200000000,
		[VDD_LOWER] = 2400000000,
		[VDD_LOW] = 3000000000,
		[VDD_NOMINAL] = 3300000000},
		},
		},
		};

		static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
		F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
		{ }
		};

		static struct clk_rcg2 gpu_cc_gmu_clk_src = {
		.cmd_rcgr = 0x1120,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gpu_cc_parent_map_0,
		.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_gmu_clk_src",
		.parent_names = gpu_cc_parent_names_0,
		.num_parents = 5,
		.ops = &clk_rcg2_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_LOWER] = 200000000},
		},
		};

		static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
		F(355200000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0),
		F(537600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
		F(672000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
		F(844800000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
		F(921600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
		F(1017600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
		F(1123200000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
		{ }
		};

		static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
		.cmd_rcgr = 0x101c,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gpu_cc_parent_map_1,
		.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_gx_gfx3d_clk_src",
		.parent_names = gpu_cc_parent_names_1,
		.num_parents = 6,
		.flags = CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
		.ops = &clk_rcg2_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_LOWER] = 355200000,
		[VDD_LOW] = 537600000,
		[VDD_LOW_L1] = 672000000,
		[VDD_NOMINAL] = 844800000,
		[VDD_NOMINAL_L1] = 921600000,
		[VDD_HIGH] = 1017600000,
		[VDD_HIGH_L1] = 1123200000},
		},
		};

		static struct clk_branch gpu_cc_ahb_clk = {
		.halt_reg = 0x1078,
		.halt_check = BRANCH_HALT_DELAY,
		.clkr = {
		.enable_reg = 0x1078,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_ahb_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_crc_ahb_clk = {
		.halt_reg = 0x107c,
		.halt_check = BRANCH_HALT_DELAY,
		.clkr = {
		.enable_reg = 0x107c,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_crc_ahb_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_cx_gfx3d_clk = {
		.halt_reg = 0x10a4,
		.halt_check = BRANCH_HALT_DELAY,
		.clkr = {
		.enable_reg = 0x10a4,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_cx_gfx3d_clk",
		.parent_names = (const char *[]){
		"gpu_cc_gx_gfx3d_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_cx_gmu_clk = {
		.halt_reg = 0x1098,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x1098,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_cx_gmu_clk",
		.parent_names = (const char *[]){
		"gpu_cc_gmu_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
		.halt_reg = 0x108c,
		.halt_check = BRANCH_HALT_DELAY,
		.clkr = {
		.enable_reg = 0x108c,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_cx_snoc_dvm_clk",
		.parent_names = (const char *[]){
		"gcc_gpu_bimc_axi_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_cxo_aon_clk = {
		.halt_reg = 0x1004,
		.halt_check = BRANCH_HALT_DELAY,
		.clkr = {
		.enable_reg = 0x1004,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_cxo_aon_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_cxo_clk = {
		.halt_reg = 0x109c,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x109c,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_cxo_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_gx_cxo_clk = {
		.halt_reg = 0x1060,
		.halt_check = BRANCH_HALT_DELAY,
		.clkr = {
		.enable_reg = 0x1060,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_gx_cxo_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_gx_gfx3d_clk = {
		.halt_reg = 0x1054,
		.halt_check = BRANCH_HALT_DELAY,
		.clkr = {
		.enable_reg = 0x1054,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_gx_gfx3d_clk",
		.parent_names = (const char *[]){
		"gpu_cc_gx_gfx3d_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
		.halt_reg = 0x5000,
		.halt_check = BRANCH_VOTED,
		.clkr = {
		.enable_reg = 0x5000,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_sleep_clk = {
		.halt_reg = 0x1090,
		.halt_check = BRANCH_VOTED,
		.clkr = {
		.enable_reg = 0x1090,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_sleep_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_regmap *gpu_cc_scuba_clocks[] = {
		[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
		[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
		[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
		[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
		[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
		[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
		[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
		[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
		[GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,
		[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
		[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
		[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
		[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
		[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
		};

		static const struct regmap_config gpu_cc_scuba_regmap_config = {
		.reg_bits = 32,
		.reg_stride = 4,
		.val_bits = 32,
		.max_register = 0x7008,
		.fast_io = true,
		};

		static const struct qcom_cc_desc gpu_cc_scuba_desc = {
		.config = &gpu_cc_scuba_regmap_config,
		.clks = gpu_cc_scuba_clocks,
		.num_clks = ARRAY_SIZE(gpu_cc_scuba_clocks),
		};

		static const struct of_device_id gpu_cc_scuba_match_table[] = {
		{ .compatible = "qcom,scuba-gpucc" },
		{ }
		};
		MODULE_DEVICE_TABLE(of, gpu_cc_scuba_match_table);

		static int gpu_cc_scuba_probe(struct platform_device *pdev)
		{
		struct regmap *regmap;
		int ret;

		vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
		if (IS_ERR(vdd_cx.regulator[0])) {
		if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER)
		dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n");
		return PTR_ERR(vdd_cx.regulator[0]);
		}

		regmap = qcom_cc_map(pdev, &gpu_cc_scuba_desc);
		if (IS_ERR(regmap))
		return PTR_ERR(regmap);

		clk_huayra_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);

		ret = qcom_cc_really_probe(pdev, &gpu_cc_scuba_desc, regmap);
		if (ret) {
		dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");
		return ret;
		}

		dev_info(&pdev->dev, "Registered GPU CC clocks\n");

		return ret;
		}

		static struct platform_driver gpu_cc_scuba_driver = {
		.probe = gpu_cc_scuba_probe,
		.driver = {
		.name = "gpu_cc-scuba",
		.of_match_table = gpu_cc_scuba_match_table,
		},
		};

		static int __init gpu_cc_scuba_init(void)
		{
		return platform_driver_register(&gpu_cc_scuba_driver);
		}
		subsys_initcall(gpu_cc_scuba_init);

		static void __exit gpu_cc_scuba_exit(void)
		{
		platform_driver_unregister(&gpu_cc_scuba_driver);
		}
		module_exit(gpu_cc_scuba_exit);

		MODULE_DESCRIPTION("QTI GPU_CC SCUBA Driver");
		MODULE_LICENSE("GPL v2");