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Commit b8ec87f6 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Mask the number of registers in the register protection span 



Make sure to mask the size of the span for protected registers to avoid
accidently messing up the rest of the bit field.  Also, set the start
and end offsets the same for the infinity span so we don't write an
underflow value to the register.

Change-Id: Ic0dedbad7eedcc6cf6cc50889f91c4b068deef2f
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent f4ba7e0f

drivers/gpu/msm/adreno-gpulist.h

+2 −2
Original line number Diff line number Diff line
@@ -766,7 +766,7 @@ static const struct a6xx_protected_regs a630_protected_regs[] = { 
	{ A6XX_CP_PROTECT_REG + 28, 0x0be20, 0x0d5ff, 1 },

	{ A6XX_CP_PROTECT_REG + 29, 0x0f000, 0x0fbff, 1 },

	{ A6XX_CP_PROTECT_REG + 30, 0x0fc00, 0x11bff, 0 },

	{ A6XX_CP_PROTECT_REG + 31, 0x11c00, 0x00000, 1 },

	{ A6XX_CP_PROTECT_REG + 31, 0x11c00, 0x11c00, 1 },

	{ 0 },

};
@@ -1019,7 +1019,7 @@ static const struct a6xx_protected_regs a620_protected_regs[] = { 
	{ A6XX_CP_PROTECT_REG + 30, 0x0be20, 0x0d5ff, 1 },

	{ A6XX_CP_PROTECT_REG + 31, 0x0f000, 0x0fbff, 1 },

	{ A6XX_CP_PROTECT_REG + 32, 0x0fc00, 0x11bff, 0 },

	{ A6XX_CP_PROTECT_REG + 47, 0x11c00, 0x00000, 1 },

	{ A6XX_CP_PROTECT_REG + 47, 0x11c00, 0x11c00, 1 },

	{ 0 },

};

drivers/gpu/msm/adreno_a6xx.c

+1 −1
Original line number Diff line number Diff line
@@ -172,7 +172,7 @@ static void a6xx_protect_init(struct adreno_device *adreno_dev) 
		count = regs[i].end - regs[i].start;



		kgsl_regwrite(device, regs[i].reg,

			regs[i].start | (count << 18) |

			(regs[i].start & 0x3ffff) | ((count & 0x1fff) << 18) |

			(regs[i].noaccess << 31));

	}

}