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Commit b8b47bfb authored by Magnus Damm's avatar Magnus Damm Committed by Paul Mundt
Browse files

sh: pass along struct pci_channel 



These patches rework the pci code for the sh architecture.

Currently each board implements some kind of ioport to address mapping.
Some boards use generic_io_base others try passing addresses as io ports.
This is the first set of patches that try to unify the pci code as much
as possible to avoid duplicated code. This will in the end lead to fewer
lines board specific code and more generic code.

This patch makes sure a struct pci_channel pointer is passed along to
various pci functions such as pci_read_reg(), pci_write_reg(),
pci_fixup_pcic(), sh7751_pcic_init() and sh7780_pcic_init().

Signed-off-by: default avatarMagnus Damm <damm@igel.co.jp>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 3ee8da87

arch/sh/drivers/pci/fixups-lboxre2.c

+12 −11
Original line number Diff line number Diff line
@@ -9,33 +9,34 @@ 
 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#include <linux/pci.h>

#include "pci-sh4.h"



#define PCIMCR_MRSET_OFF	0xBFFFFFFF

#define PCIMCR_RFSH_OFF		0xFFFFFFFB



int pci_fixup_pcic(void)

int pci_fixup_pcic(struct pci_channel *chan)

{

	unsigned long bcr1, mcr;



	bcr1 = ctrl_inl(SH7751_BCR1);

	bcr1 |= 0x40080000;	/* Enable Bit 19 BREQEN, set PCIC to slave */

	pci_write_reg(bcr1, SH4_PCIBCR1);

	pci_write_reg(chan, bcr1, SH4_PCIBCR1);



	/* Enable all interrupts, so we known what to fix */

	pci_write_reg(0x0000c3ff, SH4_PCIINTM);

	pci_write_reg(0x0000380f, SH4_PCIAINTM);

	pci_write_reg(0xfb900047, SH7751_PCICONF1);

	pci_write_reg(0xab000001, SH7751_PCICONF4);

	pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);

	pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);

	pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);

	pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);



	mcr = ctrl_inl(SH7751_MCR);

	mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;

	pci_write_reg(mcr, SH4_PCIMCR);

	pci_write_reg(chan, mcr, SH4_PCIMCR);



	pci_write_reg(0x0c000000, SH7751_PCICONF5);

	pci_write_reg(0xd0000000, SH7751_PCICONF6);

	pci_write_reg(0x0c000000, SH4_PCILAR0);

	pci_write_reg(0x00000000, SH4_PCILAR1);

	pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);

	pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);

	pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);

	pci_write_reg(chan, 0x00000000, SH4_PCILAR1);



	return 0;

}

arch/sh/drivers/pci/fixups-r7780rp.c

+17 −16
Original line number Diff line number Diff line
@@ -14,32 +14,33 @@ 
#include "pci-sh4.h"

#include <asm/io.h>



int pci_fixup_pcic(void)

int pci_fixup_pcic(struct pci_channel *chan)

{

	pci_write_reg(0x000043ff, SH4_PCIINTM);

	pci_write_reg(0x0000380f, SH4_PCIAINTM);

	pci_write_reg(chan, 0x000043ff, SH4_PCIINTM);

	pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);



	pci_write_reg(0xfbb00047, SH7780_PCICMD);

	pci_write_reg(0x00000000, SH7780_PCIIBAR);

	pci_write_reg(chan, 0xfbb00047, SH7780_PCICMD);

	pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR);



	pci_write_reg(0x00011912, SH7780_PCISVID);

	pci_write_reg(0x08000000, SH7780_PCICSCR0);

	pci_write_reg(0x0000001b, SH7780_PCICSAR0);

	pci_write_reg(0xfd000000, SH7780_PCICSCR1);

	pci_write_reg(0x0000000f, SH7780_PCICSAR1);

	pci_write_reg(chan, 0x00011912, SH7780_PCISVID);

	pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0);

	pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0);

	pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1);

	pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1);



	pci_write_reg(0xfd000000, SH7780_PCIMBR0);

	pci_write_reg(0x00fc0000, SH7780_PCIMBMR0);

	pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);

	pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);



#ifdef CONFIG_32BIT

	pci_write_reg(0xc0000000, SH7780_PCIMBR2);

	pci_write_reg(0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);

	pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);

	pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);

#endif



	/* Set IOBR for windows containing area specified in pci.h */

	pci_write_reg((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)),

	pci_write_reg(chan, (PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)),

		      SH7780_PCIIOBR);

	pci_write_reg(((SH7780_PCI_IO_SIZE-1) & (7<<18)), SH7780_PCIIOBMR);

	pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)),

		      SH7780_PCIIOBMR);



	return 0;

}

arch/sh/drivers/pci/fixups-rts7751r2d.c

+12 −11
Original line number Diff line number Diff line
@@ -10,34 +10,35 @@ 
 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#include <linux/pci.h>

#include "pci-sh4.h"



#define PCIMCR_MRSET_OFF	0xBFFFFFFF

#define PCIMCR_RFSH_OFF		0xFFFFFFFB



int pci_fixup_pcic(void)

int pci_fixup_pcic(struct pci_channel *chan)

{

	unsigned long bcr1, mcr;



	bcr1 = ctrl_inl(SH7751_BCR1);

	bcr1 |= 0x40080000;	/* Enable Bit 19 BREQEN, set PCIC to slave */

	pci_write_reg(bcr1, SH4_PCIBCR1);

	pci_write_reg(chan, bcr1, SH4_PCIBCR1);



	/* Enable all interrupts, so we known what to fix */

	pci_write_reg(0x0000c3ff, SH4_PCIINTM);

	pci_write_reg(0x0000380f, SH4_PCIAINTM);

	pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);

	pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);



	pci_write_reg(0xfb900047, SH7751_PCICONF1);

	pci_write_reg(0xab000001, SH7751_PCICONF4);

	pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);

	pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);



	mcr = ctrl_inl(SH7751_MCR);

	mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;

	pci_write_reg(mcr, SH4_PCIMCR);

	pci_write_reg(chan, mcr, SH4_PCIMCR);



	pci_write_reg(0x0c000000, SH7751_PCICONF5);

	pci_write_reg(0xd0000000, SH7751_PCICONF6);

	pci_write_reg(0x0c000000, SH4_PCILAR0);

	pci_write_reg(0x00000000, SH4_PCILAR1);

	pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);

	pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);

	pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);

	pci_write_reg(chan, 0x00000000, SH4_PCILAR1);



	return 0;

}

arch/sh/drivers/pci/fixups-sdk7780.c

+24 −22
Original line number Diff line number Diff line
@@ -14,46 +14,48 @@ 
#include "pci-sh4.h"

#include <asm/io.h>



int pci_fixup_pcic(void)

int pci_fixup_pcic(struct pci_channel *chan)

{

	ctrl_outl(0x00000001, SH7780_PCI_VCR2);



	/* Enable all interrupts, so we know what to fix */

	pci_write_reg(0x0000C3FF, SH7780_PCIIMR);

	pci_write_reg(0x0000380F, SH7780_PCIAINTM);

	pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);

	pci_write_reg(chan, 0x0000380F, SH7780_PCIAINTM);



	/* Set up standard PCI config registers */

	pci_write_reg(0xFB00, SH7780_PCISTATUS);

	pci_write_reg(0x0047, SH7780_PCICMD);

	pci_write_reg(0x00, SH7780_PCIPIF);

	pci_write_reg(0x00, SH7780_PCISUB);

	pci_write_reg(0x06, SH7780_PCIBCC);

	pci_write_reg(0x1912, SH7780_PCISVID);

	pci_write_reg(0x0001, SH7780_PCISID);

	pci_write_reg(chan, 0xFB00, SH7780_PCISTATUS);

	pci_write_reg(chan, 0x0047, SH7780_PCICMD);

	pci_write_reg(chan, 0x00, SH7780_PCIPIF);

	pci_write_reg(chan, 0x00, SH7780_PCISUB);

	pci_write_reg(chan, 0x06, SH7780_PCIBCC);

	pci_write_reg(chan, 0x1912, SH7780_PCISVID);

	pci_write_reg(chan, 0x0001, SH7780_PCISID);



	pci_write_reg(0x08000000, SH7780_PCIMBAR0);	/* PCI */

	pci_write_reg(0x08000000, SH7780_PCILAR0);	/* SHwy */

	pci_write_reg(0x07F00001, SH7780_PCILSR);	/* size 128M w/ MBAR */

	pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0);	/* PCI */

	pci_write_reg(chan, 0x08000000, SH7780_PCILAR0);	/* SHwy */

	pci_write_reg(chan, 0x07F00001, SH7780_PCILSR);	/* size 128M w/ MBAR */



	pci_write_reg(0x00000000, SH7780_PCIMBAR1);

	pci_write_reg(0x00000000, SH7780_PCILAR1);

	pci_write_reg(0x00000000, SH7780_PCILSR1);

	pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);

	pci_write_reg(chan, 0x00000000, SH7780_PCILAR1);

	pci_write_reg(chan, 0x00000000, SH7780_PCILSR1);



	pci_write_reg(0xAB000801, SH7780_PCIIBAR);

	pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);



	/*

	 * Set the MBR so PCI address is one-to-one with window,

	 * meaning all calls go straight through... use ifdef to

	 * catch erroneous assumption.

	 */

	pci_write_reg(0xFD000000 , SH7780_PCIMBR0);

	pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0);	/* 16M */

	pci_write_reg(chan, 0xFD000000 , SH7780_PCIMBR0);

	pci_write_reg(chan, 0x00FC0000 , SH7780_PCIMBMR0);	/* 16M */



	/* Set IOBR for window containing area specified in pci.h */

	pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR);

	pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR);

	pci_write_reg(chan, PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1),

		      SH7780_PCIIOBR);

	pci_write_reg(chan, (SH7780_PCI_IO_SIZE-1) & (7 << 18),

		      SH7780_PCIIOBMR);



	pci_write_reg(0xA5000C01, SH7780_PCICR);

	pci_write_reg(chan, 0xA5000C01, SH7780_PCICR);



	return 0;

}

arch/sh/drivers/pci/fixups-se7780.c

+17 −15
Original line number Diff line number Diff line
@@ -15,13 +15,13 @@ 
#include "pci-sh4.h"

#include <asm/io.h>



int pci_fixup_pcic(void)

int pci_fixup_pcic(struct pci_channel *chan)

{

	ctrl_outl(0x00000001, SH7780_PCI_VCR2);



	/* Enable all interrupts, so we know what to fix */

	pci_write_reg(0x0000C3FF, SH7780_PCIIMR);

	pci_write_reg(0x0000380F, SH7780_PCIAINTM);

	pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);

	pci_write_reg(chan, 0x0000380F, SH7780_PCIAINTM);



	/* Set up standard PCI config registers */

	ctrl_outw(0xFB00, PCI_REG(SH7780_PCISTATUS));
@@ -32,29 +32,31 @@ int pci_fixup_pcic(void) 
	ctrl_outw(0x1912, PCI_REG(SH7780_PCISVID));

	ctrl_outw(0x0001, PCI_REG(SH7780_PCISID));



	pci_write_reg(0x08000000, SH7780_PCIMBAR0);     /* PCI */

	pci_write_reg(0x08000000, SH7780_PCILAR0);     /* SHwy */

	pci_write_reg(0x07F00001, SH7780_PCILSR);      /* size 128M w/ MBAR */

	pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0);     /* PCI */

	pci_write_reg(chan, 0x08000000, SH7780_PCILAR0);     /* SHwy */

	pci_write_reg(chan, 0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */



	pci_write_reg(0x00000000, SH7780_PCIMBAR1);

	pci_write_reg(0x00000000, SH7780_PCILAR1);

	pci_write_reg(0x00000000, SH7780_PCILSR1);

	pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);

	pci_write_reg(chan, 0x00000000, SH7780_PCILAR1);

	pci_write_reg(chan, 0x00000000, SH7780_PCILSR1);



	pci_write_reg(0xAB000801, SH7780_PCIIBAR);

	pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);



	/*

	 * Set the MBR so PCI address is one-to-one with window,

	 * meaning all calls go straight through... use ifdef to

	 * catch erroneous assumption.

	 */

	pci_write_reg(0xFD000000 , SH7780_PCIMBR0);

	pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0);    /* 16M */

	pci_write_reg(chan, 0xFD000000 , SH7780_PCIMBR0);

	pci_write_reg(chan, 0x00FC0000 , SH7780_PCIMBMR0);    /* 16M */



	/* Set IOBR for window containing area specified in pci.h */

	pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR);

	pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR);

	pci_write_reg(chan, PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1),

		      SH7780_PCIIOBR);

	pci_write_reg(chan, (SH7780_PCI_IO_SIZE-1) & (7 << 18),

		      SH7780_PCIIOBMR);



	pci_write_reg(0xA5000C01, SH7780_PCICR);

	pci_write_reg(chan, 0xA5000C01, SH7780_PCICR);



	return 0;

}