Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b891b4dc authored by Jingoo Han's avatar Jingoo Han Committed by Bjorn Helgaas
Browse files

PCI: Fix bit definitions of PCI_EXP_LNKCAP2 register 



According to the PCIe 3.0 spec, PCI_EXP_LNKCAP2_SLS_2_5GB is
1st bit of PCI_EXP_LNKCAP2 register, not 0th bit. So, the bit
definition of supported link speed vector should be fixed.

[bhelgaas: change "Current" to "Supported"]
Signed-off-by: default avatarJingoo Han <jg1.han@samsung.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 6e965e0d

include/uapi/linux/pci_regs.h

+3 −3
Original line number Diff line number Diff line
@@ -544,9 +544,9 @@ 
#define  PCI_EXP_OBFF_WAKE_EN	0x6000	/* OBFF using WAKE# signaling */

#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2	44	/* v2 endpoints end here */

#define PCI_EXP_LNKCAP2		44	/* Link Capability 2 */

#define  PCI_EXP_LNKCAP2_SLS_2_5GB 0x01	/* Current Link Speed 2.5GT/s */

#define  PCI_EXP_LNKCAP2_SLS_5_0GB 0x02	/* Current Link Speed 5.0GT/s */

#define  PCI_EXP_LNKCAP2_SLS_8_0GB 0x04	/* Current Link Speed 8.0GT/s */

#define  PCI_EXP_LNKCAP2_SLS_2_5GB 0x02	/* Supported Link Speed 2.5GT/s */

#define  PCI_EXP_LNKCAP2_SLS_5_0GB 0x04	/* Supported Link Speed 5.0GT/s */

#define  PCI_EXP_LNKCAP2_SLS_8_0GB 0x08	/* Supported Link Speed 8.0GT/s */

#define  PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */

#define PCI_EXP_LNKCTL2		48	/* Link Control 2 */

#define PCI_EXP_LNKSTA2		50	/* Link Status 2 */