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Commit b87d78d6 authored by Yue Hin Lau's avatar Yue Hin Lau Committed by Alex Deucher
Browse files

drm/amd/display: moving cursor functions from ipp to mem_input 



Signed-off-by: default avatarYue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 60d671db

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

+27 −5
Original line number Diff line number Diff line
@@ -195,13 +195,23 @@ bool dc_stream_set_cursor_attributes( 
	for (i = 0; i < MAX_PIPES; i++) {

		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];



		if (pipe_ctx->stream != stream || !pipe_ctx->plane_res.ipp)

		if (pipe_ctx->stream != stream || !pipe_ctx->plane_res.mi || !pipe_ctx->plane_res.xfm)

			continue;

		if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)

			continue;





		if (pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes != NULL)

			pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(

						pipe_ctx->plane_res.ipp, attributes);



		if (pipe_ctx->plane_res.mi->funcs->set_cursor_attributes != NULL)

			pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(

					pipe_ctx->plane_res.mi, attributes);



		if (pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes != NULL)

			pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(

				pipe_ctx->plane_res.xfm, attributes);

	}



	return true;
@@ -231,6 +241,8 @@ bool dc_stream_set_cursor_position( 
	for (i = 0; i < MAX_PIPES; i++) {

		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

		struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;

		struct mem_input *mi = pipe_ctx->plane_res.mi;

		struct transform *xfm = pipe_ctx->plane_res.xfm;

		struct dc_cursor_position pos_cpy = *position;

		struct dc_cursor_mi_param param = {

			.pixel_clk_khz = stream->timing.pix_clk_khz,
@@ -241,7 +253,9 @@ bool dc_stream_set_cursor_position( 
		};



		if (pipe_ctx->stream != stream ||

				!pipe_ctx->plane_res.ipp || !pipe_ctx->plane_state)

				!pipe_ctx->plane_res.mi ||

				!pipe_ctx->plane_state ||

				!pipe_ctx->plane_res.xfm)

			continue;



		if (pipe_ctx->plane_state->address.type
@@ -251,7 +265,15 @@ bool dc_stream_set_cursor_position( 
		if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)

			pos_cpy.enable = false;





		if (ipp->funcs->ipp_cursor_set_position != NULL)

			ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);



		if (mi->funcs->set_cursor_attributes != NULL)

			mi->funcs->set_cursor_position(mi, &pos_cpy, &param);



		if (xfm->funcs->set_cursor_attributes != NULL)

			xfm->funcs->set_cursor_position(xfm, &pos_cpy, &param, mi->curs_attr.width);

	}



	return true;

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

+2 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
#define CTX \

	ipp_dce->base.ctx





static void dce_ipp_cursor_set_position(

	struct input_pixel_processor *ipp,

	const struct dc_cursor_position *position,
@@ -133,6 +134,7 @@ static void dce_ipp_cursor_set_attributes( 
	REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);

}





static void dce_ipp_program_prescale(

	struct input_pixel_processor *ipp,

	struct ipp_prescale_params *params)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c

+51 −0
Original line number Diff line number Diff line
@@ -372,6 +372,55 @@ void ippn10_cnv_setup ( 
	}

}



void dcn10_set_cursor_attributes(

		struct transform *xfm_base,

		const struct dc_cursor_attributes *attr)

{

	struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base);

	enum dc_cursor_color_format color_format = attr->color_format;



	REG_UPDATE_2(CURSOR0_CONTROL,

			CUR0_MODE, color_format,

			CUR0_EXPANSION_MODE, 0);



	if (color_format == CURSOR_MODE_MONO) {

		/* todo: clarify what to program these to */

		REG_UPDATE(CURSOR0_COLOR0,

				CUR0_COLOR0, 0x00000000);

		REG_UPDATE(CURSOR0_COLOR1,

				CUR0_COLOR1, 0xFFFFFFFF);

	}



	/* TODO: Fixed vs float */



	REG_UPDATE_3(FORMAT_CONTROL,

				CNVC_BYPASS, 0,

				FORMAT_CONTROL__ALPHA_EN, 1,

				FORMAT_EXPANSION_MODE, 0);

}





void dcn10_set_cursor_position(

		struct transform *xfm_base,

		const struct dc_cursor_position *pos,

		const struct dc_cursor_mi_param *param,

		uint32_t width)

{

	struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base);

	int src_x_offset = pos->x - pos->x_hotspot - param->viewport_x_start;

	uint32_t cur_en = pos->enable ? 1 : 0;



	if (src_x_offset >= (int)param->viewport_width)

		cur_en = 0;  /* not visible beyond right edge*/



	if (src_x_offset + (int)width < 0)

		cur_en = 0;  /* not visible beyond left edge*/



	REG_UPDATE(CURSOR0_CONTROL,

			CUR0_ENABLE, cur_en);



}



static const struct transform_funcs dcn10_dpp_funcs = {

		.transform_reset = dpp_reset,

		.transform_set_scaler = dcn10_dpp_dscl_set_scaler_manual_scale,
@@ -391,6 +440,8 @@ static const struct transform_funcs dcn10_dpp_funcs = { 
		.ipp_program_degamma_pwl	= ippn10_set_degamma_pwl,

		.ipp_setup			= ippn10_cnv_setup,

		.ipp_full_bypass		= ippn10_full_bypass,

		.set_cursor_attributes = dcn10_set_cursor_attributes,

		.set_cursor_position = dcn10_set_cursor_position,

};

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h

+12 −3
Original line number Diff line number Diff line
@@ -112,7 +112,10 @@ 
	SRI(CM_DGAM_CONTROL, CM, id), \

	SRI(FORMAT_CONTROL, CNVC_CFG, id), \

	SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \

	SRI(CURSOR0_CONTROL, CNVC_CUR, id)

	SRI(CURSOR0_CONTROL, CNVC_CUR, id), \

	SRI(CURSOR0_CONTROL, CNVC_CUR, id), \

	SRI(CURSOR0_COLOR0, CNVC_CUR, id), \

	SRI(CURSOR0_COLOR1, CNVC_CUR, id)
@@ -302,7 +305,9 @@ 
	TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \

	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \

	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \

	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh)

	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \

	TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \

	TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh)



#define TF_REG_LIST_SH_MASK_DCN10(mask_sh)\

	TF_REG_LIST_SH_MASK_DCN(mask_sh),\
@@ -989,7 +994,9 @@ 
	type CUR0_EXPANSION_MODE; \

	type CUR0_ENABLE; \

	type CM_BYPASS; \

	type FORMAT_CONTROL__ALPHA_EN

	type FORMAT_CONTROL__ALPHA_EN; \

	type CUR0_COLOR0; \

	type CUR0_COLOR1
@@ -1237,6 +1244,8 @@ struct dcn_dpp_registers { 
	uint32_t CNVC_SURFACE_PIXEL_FORMAT;

	uint32_t CURSOR_CONTROL;

	uint32_t CURSOR0_CONTROL;

	uint32_t CURSOR0_COLOR0;

	uint32_t CURSOR0_COLOR1;

};



struct dcn10_dpp {

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c

+0 −189
Original line number Diff line number Diff line
@@ -37,188 +37,6 @@ 
#define CTX \

	ippn10->base.ctx



static bool ippn10_cursor_program_control(

		struct dcn10_ipp *ippn10,

		bool pixel_data_invert,

		enum dc_cursor_color_format color_format)

{

	if (REG(CURSOR_SETTINS))

		REG_SET_2(CURSOR_SETTINS, 0,

				/* no shift of the cursor HDL schedule */

				CURSOR0_DST_Y_OFFSET, 0,

				 /* used to shift the cursor chunk request deadline */

				CURSOR0_CHUNK_HDL_ADJUST, 3);

	else

		REG_SET_2(CURSOR_SETTINGS, 0,

				/* no shift of the cursor HDL schedule */

				CURSOR0_DST_Y_OFFSET, 0,

				 /* used to shift the cursor chunk request deadline */

				CURSOR0_CHUNK_HDL_ADJUST, 3);



	REG_UPDATE_2(CURSOR0_CONTROL,

			CUR0_MODE, color_format,

			CUR0_EXPANSION_MODE, 0);



	if (color_format == CURSOR_MODE_MONO) {

		/* todo: clarify what to program these to */

		REG_UPDATE(CURSOR0_COLOR0,

				CUR0_COLOR0, 0x00000000);

		REG_UPDATE(CURSOR0_COLOR1,

				CUR0_COLOR1, 0xFFFFFFFF);

	}



	/* TODO: Fixed vs float */



	REG_UPDATE_3(FORMAT_CONTROL,

				CNVC_BYPASS, 0,

				ALPHA_EN, 1,

				FORMAT_EXPANSION_MODE, 0);



	return true;

}



enum cursor_pitch {

	CURSOR_PITCH_64_PIXELS = 0,

	CURSOR_PITCH_128_PIXELS,

	CURSOR_PITCH_256_PIXELS

};



enum cursor_lines_per_chunk {

	CURSOR_LINE_PER_CHUNK_2 = 1,

	CURSOR_LINE_PER_CHUNK_4,

	CURSOR_LINE_PER_CHUNK_8,

	CURSOR_LINE_PER_CHUNK_16

};



static enum cursor_pitch ippn10_get_cursor_pitch(

		unsigned int pitch)

{

	enum cursor_pitch hw_pitch;



	switch (pitch) {

	case 64:

		hw_pitch = CURSOR_PITCH_64_PIXELS;

		break;

	case 128:

		hw_pitch = CURSOR_PITCH_128_PIXELS;

		break;

	case 256:

		hw_pitch = CURSOR_PITCH_256_PIXELS;

		break;

	default:

		DC_ERR("Invalid cursor pitch of %d. "

				"Only 64/128/256 is supported on DCN.\n", pitch);

		hw_pitch = CURSOR_PITCH_64_PIXELS;

		break;

	}

	return hw_pitch;

}



static enum cursor_lines_per_chunk ippn10_get_lines_per_chunk(

		unsigned int cur_width,

		enum dc_cursor_color_format format)

{

	enum cursor_lines_per_chunk line_per_chunk;



	if (format == CURSOR_MODE_MONO)

		/* impl B. expansion in CUR Buffer reader */

		line_per_chunk = CURSOR_LINE_PER_CHUNK_16;

	else if (cur_width <= 32)

		line_per_chunk = CURSOR_LINE_PER_CHUNK_16;

	else if (cur_width <= 64)

		line_per_chunk = CURSOR_LINE_PER_CHUNK_8;

	else if (cur_width <= 128)

		line_per_chunk = CURSOR_LINE_PER_CHUNK_4;

	else

		line_per_chunk = CURSOR_LINE_PER_CHUNK_2;



	return line_per_chunk;

}



static void ippn10_cursor_set_attributes(

		struct input_pixel_processor *ipp,

		const struct dc_cursor_attributes *attr)

{

	struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);

	enum cursor_pitch hw_pitch = ippn10_get_cursor_pitch(attr->pitch);

	enum cursor_lines_per_chunk lpc = ippn10_get_lines_per_chunk(

			attr->width, attr->color_format);



	ippn10->curs_attr = *attr;



	REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,

			CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);

	REG_UPDATE(CURSOR_SURFACE_ADDRESS,

			CURSOR_SURFACE_ADDRESS, attr->address.low_part);



	REG_UPDATE_2(CURSOR_SIZE,

			CURSOR_WIDTH, attr->width,

			CURSOR_HEIGHT, attr->height);

	REG_UPDATE_3(CURSOR_CONTROL,

			CURSOR_MODE, attr->color_format,

			CURSOR_PITCH, hw_pitch,

			CURSOR_LINES_PER_CHUNK, lpc);

	ippn10_cursor_program_control(ippn10,

			attr->attribute_flags.bits.INVERT_PIXEL_DATA,

			attr->color_format);

}



static void ippn10_cursor_set_position(

		struct input_pixel_processor *ipp,

		const struct dc_cursor_position *pos,

		const struct dc_cursor_mi_param *param)

{

	struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);

	int src_x_offset = pos->x - pos->x_hotspot - param->viewport_x_start;

	uint32_t cur_en = pos->enable ? 1 : 0;

	uint32_t dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;



	/*

	 * Guard aganst cursor_set_position() from being called with invalid

	 * attributes

	 *

	 * TODO: Look at combining cursor_set_position() and

	 * cursor_set_attributes() into cursor_update()

	 */

	if (ippn10->curs_attr.address.quad_part == 0)

		return;



	dst_x_offset *= param->ref_clk_khz;

	dst_x_offset /= param->pixel_clk_khz;



	ASSERT(param->h_scale_ratio.value);



	if (param->h_scale_ratio.value)

		dst_x_offset = dal_fixed31_32_floor(dal_fixed31_32_div(

				dal_fixed31_32_from_int(dst_x_offset),

				param->h_scale_ratio));



	if (src_x_offset >= (int)param->viewport_width)

		cur_en = 0;  /* not visible beyond right edge*/



	if (src_x_offset + (int)ippn10->curs_attr.width < 0)

		cur_en = 0;  /* not visible beyond left edge*/



	if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)

		ippn10_cursor_set_attributes(ipp, &ippn10->curs_attr);

	REG_UPDATE(CURSOR_CONTROL,

			CURSOR_ENABLE, cur_en);

	REG_UPDATE(CURSOR0_CONTROL,

			CUR0_ENABLE, cur_en);



	REG_SET_2(CURSOR_POSITION, 0,

			CURSOR_X_POSITION, pos->x,

			CURSOR_Y_POSITION, pos->y);



	REG_SET_2(CURSOR_HOT_SPOT, 0,

			CURSOR_HOT_SPOT_X, pos->x_hotspot,

			CURSOR_HOT_SPOT_Y, pos->y_hotspot);



	REG_SET(CURSOR_DST_OFFSET, 0,

			CURSOR_DST_X_OFFSET, dst_x_offset);

	/* TODO Handle surface pixel formats other than 4:4:4 */

}



/*****************************************/

/* Constructor, Destructor               */

/*****************************************/
@@ -230,13 +48,6 @@ static void dcn10_ipp_destroy(struct input_pixel_processor **ipp) 
}



static const struct ipp_funcs dcn10_ipp_funcs = {

	.ipp_cursor_set_attributes	= ippn10_cursor_set_attributes,

	.ipp_cursor_set_position	= ippn10_cursor_set_position,

	.ipp_set_degamma		= NULL,

	.ipp_program_input_lut		= NULL,

	.ipp_full_bypass		= NULL,

	.ipp_setup			= NULL,

	.ipp_program_degamma_pwl	= NULL,

	.ipp_destroy			= dcn10_ipp_destroy

};