Merge branch 'linus' into x86/urgent

ffffffbe00000000	ffffffbffbbfffff	  ~8GB		[guard, future vmmemap]

ffffffbffbc00000	ffffffbffbdfffff	   2MB		earlyprintk device

ffffffbffa000000	ffffffbffaffffff	  16MB		PCI I/O space

ffffffbffb000000	ffffffbffbbfffff	  12MB		[guard]

ffffffbffbe00000	ffffffbffbe0ffff	  64KB		PCI I/O space

ffffffbffbc00000	ffffffbffbdfffff	   2MB		earlyprintk device

ffffffbffbe10000	ffffffbcffffffff	  ~2MB		[guard]

ffffffbffbe00000	ffffffbffbffffff	   2MB		[guard]

ffffffbffc000000	ffffffbfffffffff	  64MB		modules

fffffdfe00000000	fffffdfffbbfffff	  ~8GB		[guard, future vmmemap]

fffffdfffbc00000	fffffdfffbdfffff	   2MB		earlyprintk device

fffffdfffa000000	fffffdfffaffffff	  16MB		PCI I/O space

fffffdfffb000000	fffffdfffbbfffff	  12MB		[guard]

fffffdfffbe00000	fffffdfffbe0ffff	  64KB		PCI I/O space

fffffdfffbc00000	fffffdfffbdfffff	   2MB		earlyprintk device

fffffdfffbe10000	fffffdfffbffffff	  ~2MB		[guard]

fffffdfffbe00000	fffffdfffbffffff	   2MB		[guard]

fffffdfffc000000	fffffdffffffffff	  64MB		modules

Marvell Armada 370 and Armada XP Interrupt Controller

Marvell Armada 370, 375, 38x, XP Interrupt Controller

-----------------------------------------------------

Required properties:

  automatically map to the interrupt controller registers of the

  current CPU)

Optional properties:

- interrupts: If defined, then it indicates that this MPIC is

  connected as a slave to another interrupt controller. This is

  typically the case on Armada 375 and Armada 38x, where the MPIC is

  connected as a slave to the Cortex-A9 GIC. The provided interrupt

  indicate to which GIC interrupt the MPIC output is connected.

Example:

Each SATA controller should have its own node.

Required properties:

- compatible        : compatible list, contains "snps,spear-ahci"

- compatible        : compatible list, one of "snps,spear-ahci",

                      "snps,exynos5440-ahci", "ibm,476gtr-ahci",

                      "allwinner,sun4i-a10-ahci", "fsl,imx53-ahci"

                      "fsl,imx6q-ahci" or "snps,dwc-ahci"

- interrupts        : <interrupt mapping for SATA IRQ>

- reg               : <registers mapping>

Optional properties:

- dma-coherent      : Present if dma operations are coherent

- clocks            : a list of phandle + clock specifier pairs

- target-supply     : regulator for SATA target power

Example:

"fsl,imx53-ahci", "fsl,imx6q-ahci" required properties:

- clocks            : must contain the sata, sata_ref and ahb clocks

- clock-names       : must contain "ahb" for the ahb clock

Examples:

        sata@ffe08000 {

		compatible = "snps,spear-ahci";

		reg = <0xffe08000 0x1000>;

		interrupts = <115>;

        };

	ahci: sata@01c18000 {

		compatible = "allwinner,sun4i-a10-ahci";

		reg = <0x01c18000 0x1000>;

		interrupts = <56>;

		clocks = <&pll6 0>, <&ahb_gates 25>;

		target-supply = <&reg_ahci_5v>;

	};

* APM X-Gene 6.0 Gb/s SATA host controller nodes

SATA host controller nodes are defined to describe on-chip Serial ATA

controllers. Each SATA controller (pair of ports) have its own node.

Required properties:

- compatible		: Shall contain:

  * "apm,xgene-ahci"

- reg			: First memory resource shall be the AHCI memory

			  resource.

			  Second memory resource shall be the host controller

			  core memory resource.

			  Third memory resource shall be the host controller

			  diagnostic memory resource.

			  4th memory resource shall be the host controller

			  AXI memory resource.

			  5th optional memory resource shall be the host

			  controller MUX memory resource if required.

- interrupts		: Interrupt-specifier for SATA host controller IRQ.

- clocks		: Reference to the clock entry.

- phys			: A list of phandles + phy-specifiers, one for each

			  entry in phy-names.

- phy-names		: Should contain:

  * "sata-phy" for the SATA 6.0Gbps PHY

Optional properties:

- status		: Shall be "ok" if enabled or "disabled" if disabled.

			  Default is "ok".

Example:

		sataclk: sataclk {

			compatible = "fixed-clock";

			#clock-cells = <1>;

			clock-frequency = <100000000>;

			clock-output-names = "sataclk";

		};

		phy2: phy@1f22a000 {

			compatible = "apm,xgene-phy";

			reg = <0x0 0x1f22a000 0x0 0x100>;

			#phy-cells = <1>;

		};

		phy3: phy@1f23a000 {

			compatible = "apm,xgene-phy";

			reg = <0x0 0x1f23a000 0x0 0x100>;

			#phy-cells = <1>;

		};

		sata2: sata@1a400000 {

			compatible = "apm,xgene-ahci";

			reg = <0x0 0x1a400000 0x0 0x1000>,

			      <0x0 0x1f220000 0x0 0x1000>,

			      <0x0 0x1f22d000 0x0 0x1000>,

			      <0x0 0x1f22e000 0x0 0x1000>,

			      <0x0 0x1f227000 0x0 0x1000>;

			interrupts = <0x0 0x87 0x4>;

			status = "ok";

			clocks = <&sataclk 0>;

			phys = <&phy2 0>;

			phy-names = "sata-phy";

		};

		sata3: sata@1a800000 {

			compatible = "apm,xgene-ahci-pcie";

			reg = <0x0 0x1a800000 0x0 0x1000>,

			      <0x0 0x1f230000 0x0 0x1000>,

			      <0x0 0x1f23d000 0x0 0x1000>,

			      <0x0 0x1f23e000 0x0 0x1000>,

			      <0x0 0x1f237000 0x0 0x1000>;

			interrupts = <0x0 0x88 0x4>;

			status = "ok";

			clocks = <&sataclk 0>;

			phys = <&phy3 0>;

			phy-names = "sata-phy";

		};

Required properties:

- compatible : should be "allwinner,sun4i-ic"

- compatible : should be "allwinner,sun4i-a10-ic"

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

Example:

intc: interrupt-controller {

	compatible = "allwinner,sun4i-ic";

	compatible = "allwinner,sun4i-a10-ic";

	reg = <0x01c20400 0x400>;

	interrupt-controller;

	#interrupt-cells = <1>;