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Commit b83d4310 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: gpucc: Add support for HLOS1_VOTE_GPU_SMMU_CLK"

parents 2fd0633d 1ef5f63f
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+14 −0
Original line number Diff line number Diff line
@@ -338,6 +338,19 @@ static struct clk_branch gpu_cc_sleep_clk = {
	},
};

static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
	.halt_reg = 0x5000,
	.halt_check = BRANCH_VOTED,
	.clkr = {
		.enable_reg = 0x5000,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
			 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
			 .ops = &clk_branch2_ops,
		},
	},
};

static struct clk_regmap *gpu_cc_kona_clocks[] = {
	[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
@@ -355,6 +368,7 @@ static struct clk_regmap *gpu_cc_kona_clocks[] = {
	[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
	[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
	[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
	[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
};

static const struct qcom_reset_map gpu_cc_kona_resets[] = {
+14 −0
Original line number Diff line number Diff line
@@ -326,6 +326,19 @@ static struct clk_branch gpu_cc_sleep_clk = {
	},
};

static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
	.halt_reg = 0x5000,
	.halt_check = BRANCH_VOTED,
	.clkr = {
		.enable_reg = 0x5000,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
			 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
			 .ops = &clk_branch2_ops,
		},
	},
};

static struct clk_regmap *gpu_cc_lito_clocks[] = {
	[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
@@ -341,6 +354,7 @@ static struct clk_regmap *gpu_cc_lito_clocks[] = {
	[GPU_CC_RBCPR_CLK] = &gpu_cc_rbcpr_clk.clkr,
	[GPU_CC_RBCPR_CLK_SRC] = &gpu_cc_rbcpr_clk_src.clkr,
	[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
	[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
};

static const struct regmap_config gpu_cc_lito_regmap_config = {
+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@
#define GPU_CC_GX_VSENSE_CLK					13
#define GPU_CC_PLL1						14
#define GPU_CC_SLEEP_CLK					15
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK				16

#define CX_GDSC							0
#define GX_GDSC							1
+1 −0
Original line number Diff line number Diff line
@@ -19,5 +19,6 @@
#define GPU_CC_RBCPR_CLK					11
#define GPU_CC_RBCPR_CLK_SRC					12
#define GPU_CC_SLEEP_CLK					13
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK				14

#endif