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Commit b82ed43d authored by Lionel Landwerlin's avatar Lionel Landwerlin
Browse files

drm/i915: rename PPGTT/GGTT fields OA registers 



We had a generic field name used across 2 registers but it feels like
it's clearer we make it obvious what register this field belongs to.

Signed-off-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180326090831.22686-7-lionel.g.landwerlin@intel.com
parent 53744104

drivers/gpu/drm/i915/i915_perf.c

+4 −3
Original line number Diff line number Diff line
@@ -1043,7 +1043,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream *stream, 


		I915_WRITE(GEN7_OASTATUS2,

			   ((head & GEN7_OASTATUS2_HEAD_MASK) |

			    OA_MEM_SELECT_GGTT));

			    GEN7_OASTATUS2_MEM_SELECT_GGTT));

		dev_priv->perf.oa.oa_buffer.head = head;



		spin_unlock_irqrestore(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
@@ -1333,7 +1333,8 @@ static void gen7_init_oa_buffer(struct drm_i915_private *dev_priv) 
	/* Pre-DevBDW: OABUFFER must be set with counters off,

	 * before OASTATUS1, but after OASTATUS2

	 */

	I915_WRITE(GEN7_OASTATUS2, gtt_offset | OA_MEM_SELECT_GGTT); /* head */

	I915_WRITE(GEN7_OASTATUS2,

		   gtt_offset | GEN7_OASTATUS2_MEM_SELECT_GGTT); /* head */

	dev_priv->perf.oa.oa_buffer.head = gtt_offset;



	I915_WRITE(GEN7_OABUFFER, gtt_offset);
@@ -1393,7 +1394,7 @@ static void gen8_init_oa_buffer(struct drm_i915_private *dev_priv) 
	 *  bit."

	 */

	I915_WRITE(GEN8_OABUFFER, gtt_offset |

		   OABUFFER_SIZE_16M | OA_MEM_SELECT_GGTT);

		   OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);

	I915_WRITE(GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK);



	/* Mark that we need updated tail pointers to read from... */

drivers/gpu/drm/i915/i915_reg.h

+3 −3
Original line number Diff line number Diff line
@@ -536,6 +536,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 


#define GEN8_OABUFFER_UDW _MMIO(0x23b4)

#define GEN8_OABUFFER _MMIO(0x2b14)

#define  GEN8_OABUFFER_MEM_SELECT_GGTT      (1 << 0)  /* 0: PPGTT, 1: GGTT */



#define GEN7_OASTATUS1 _MMIO(0x2364)

#define  GEN7_OASTATUS1_TAIL_MASK	    0xffffffc0
@@ -545,6 +546,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 


#define GEN7_OASTATUS2 _MMIO(0x2368)

#define  GEN7_OASTATUS2_HEAD_MASK           0xffffffc0

#define  GEN7_OASTATUS2_MEM_SELECT_GGTT     (1 << 0) /* 0: PPGTT, 1: GGTT */



#define GEN8_OASTATUS _MMIO(0x2b08)

#define  GEN8_OASTATUS_OVERRUN_STATUS	    (1<<3)
@@ -566,8 +568,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define OABUFFER_SIZE_8M    (6<<3)

#define OABUFFER_SIZE_16M   (7<<3)



#define OA_MEM_SELECT_GGTT  (1<<0)



/*

 * Flexible, Aggregate EU Counter Registers.

 * Note: these aren't contiguous