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Commit b80c6698 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: update mdss byte/pxl clocks for SPF targets"

parents 71e94454 9d088612

qcom/msm8917-mdss.dtsi

+0 −1
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#include "msm8937-mdss.dtsi"

#include <dt-bindings/clock/mdss-28nm-pll-clk.h>

&mdss_dsi {

	vdda-supply = <&pm8937_l2>;

	vddio-supply = <&pm8937_l6>;

qcom/msm8917.dtsi

+1 −1
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#include "skeleton64.dtsi"

#include <dt-bindings/clock/qcom,gcc-sdm429w.h>

#include <dt-bindings/clock/mdss-28nm-pll-clk.h>

#include <dt-bindings/clock/mdss-28nm-pll-clk-legacy.h>

#include <dt-bindings/clock/qcom,cpu-sdm.h>

#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>

qcom/msm8937-mdss.dtsi

+6 −7
Original line number Diff line number Diff line
@@ -234,13 +234,12 @@ 


		clocks = <&gcc_mdss MDSS_MDP_VOTE_CLK>,

			<&gcc GCC_MDSS_AHB_CLK>,

			<&gcc GCC_MDSS_AXI_CLK>;

			/* TODO

			 * <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>,

			 * <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>,

			 * <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>,

			 * <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>;

			 */

			<&gcc GCC_MDSS_AXI_CLK>,

			<&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,

			<&mdss_dsi1_pll BYTECLK_SRC_1_CLK>,

			<&mdss_dsi0_pll PCLK_SRC_0_CLK>,

			<&mdss_dsi1_pll PCLK_SRC_1_CLK>;



		clock-names = "mdp_core_clk", "iface_clk", "bus_clk",

			"ext_byte0_clk", "ext_byte1_clk", "ext_pixel0_clk",

			"ext_pixel1_clk";

qcom/msm8937.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,gcc-sdm429w.h>

#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/clock/mdss-28nm-pll-clk.h>

#include <dt-bindings/clock/mdss-28nm-pll-clk-legacy.h>



#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))

#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
@@ -599,10 +599,10 @@ 
	gcc_mdss: qcom,gcc-mdss@1800000 {

		compatible = "qcom,gcc-mdss-msm8937";

		reg = <0x1800000 0x80000>;

		 clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>,

		 <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>,

		 <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>,

		 <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>;

		 clocks = <&mdss_dsi0_pll PCLK_SRC_0_CLK>,

		 <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,

		 <&mdss_dsi1_pll PCLK_SRC_1_CLK>,

		 <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>;

		clock-names = "pclk0_src", "byte0_src", "pclk1_src",

			"byte1_src";

		#clock-cells = <1>;

qcom/sdm429.dtsi

+4 −6
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@@ -219,12 +219,10 @@ 


&gcc_mdss {

	compatible = "qcom,gcc-mdss-sdm429";

	/* TODO

	 * clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>,

	 * <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>,

	 * <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>,

	 * <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>;

	 */

	clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>,

		<&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>,

		<&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>,

		<&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>;

	clock-names = "pclk0_src", "byte0_src", "pclk1_src",

		"byte1_src";

	#clock-cells = <1>;