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Commit b7ea139a authored by Sujeev Dias's avatar Sujeev Dias
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mhi: core: force wake when exiting MHI suspend (M3) state



It's possible for MHI host to exit M3 and enter low power mode
by the time resume thread wakes up from M0 signal. To prevent
transitioning into low power mode, keep wake asserted until
host wakes up from M0 signal transition.

CRs-Fixed: 2360155
Change-Id: If94b3a23eeda711bd70932279e60bcb80c465b31
Signed-off-by: default avatarSujeev Dias <sdias@codeaurora.org>
parent cf071408
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+1 −1
Original line number Original line Diff line number Diff line
@@ -440,7 +440,7 @@ enum MHI_PM_STATE {
#define MHI_PM_IN_FATAL_STATE(pm_state) (pm_state == MHI_PM_LD_ERR_FATAL_DETECT)
#define MHI_PM_IN_FATAL_STATE(pm_state) (pm_state == MHI_PM_LD_ERR_FATAL_DETECT)
#define MHI_DB_ACCESS_VALID(pm_state) (pm_state & MHI_PM_M0)
#define MHI_DB_ACCESS_VALID(pm_state) (pm_state & MHI_PM_M0)
#define MHI_WAKE_DB_CLEAR_VALID(pm_state) (pm_state & (MHI_PM_M0 | \
#define MHI_WAKE_DB_CLEAR_VALID(pm_state) (pm_state & (MHI_PM_M0 | \
						       MHI_PM_M2))
						MHI_PM_M2 | MHI_PM_M3_EXIT))
#define MHI_WAKE_DB_SET_VALID(pm_state) (pm_state & MHI_PM_M2)
#define MHI_WAKE_DB_SET_VALID(pm_state) (pm_state & MHI_PM_M2)
#define MHI_WAKE_DB_FORCE_SET_VALID(pm_state) MHI_WAKE_DB_CLEAR_VALID(pm_state)
#define MHI_WAKE_DB_FORCE_SET_VALID(pm_state) MHI_WAKE_DB_CLEAR_VALID(pm_state)
#define MHI_EVENT_ACCESS_INVALID(pm_state) (pm_state == MHI_PM_DISABLE || \
#define MHI_EVENT_ACCESS_INVALID(pm_state) (pm_state == MHI_PM_DISABLE || \
+5 −0
Original line number Original line Diff line number Diff line
@@ -1014,6 +1014,7 @@ int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
	}
	}


	/* set dev to M0 and wait for completion */
	/* set dev to M0 and wait for completion */
	mhi_cntrl->wake_get(mhi_cntrl, true);
	mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
	mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
	write_unlock_irq(&mhi_cntrl->pm_lock);
	write_unlock_irq(&mhi_cntrl->pm_lock);


@@ -1022,6 +1023,10 @@ int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
				 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
				 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
				 msecs_to_jiffies(mhi_cntrl->timeout_ms));
				 msecs_to_jiffies(mhi_cntrl->timeout_ms));


	read_lock_bh(&mhi_cntrl->pm_lock);
	mhi_cntrl->wake_put(mhi_cntrl, false);
	read_unlock_bh(&mhi_cntrl->pm_lock);

	if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
	if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
		MHI_ERR("Did not enter M0 state, cur_state:%s pm_state:%s\n",
		MHI_ERR("Did not enter M0 state, cur_state:%s pm_state:%s\n",
			TO_MHI_STATE_STR(mhi_cntrl->dev_state),
			TO_MHI_STATE_STR(mhi_cntrl->dev_state),