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Commit b7dccbea authored by Thomas Gleixner's avatar Thomas Gleixner
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Merge tag 'irqchip-core-4.1-3' of git://git.infradead.org/users/jcooper/linux into irq/core 

irqchip core change for v4.1 (round 3) from Jason Cooper

 Purge the gic_arch_extn hacks and abuse by using the new stacked domains

   NOTE: Due to the nature of these changes, patches crossing subsystems have
         been kept together in their own branches.

    - tegra
       - Handle the LIC properly

    - omap
       - Convert crossbar to stacked domains
       - kill arm,routable-irqs in GIC binding

    - exynos
       - Convert PMU wakeup to stacked domains

    - shmobile, ux500, zynq (irq_set_wake branch)
       - Switch from abusing gic_arch_extn to using gic_set_irqchip_flags
parents 425b655c a01e7b32

Documentation/devicetree/bindings/arm/gic.txt

+0 −6
Original line number Original line Diff line number Diff line
@@ -56,11 +56,6 @@ Optional 
  regions, used when the GIC doesn't have banked registers. The offset is

  regions, used when the GIC doesn't have banked registers. The offset is

  cpu-offset * cpu-nr.

  cpu-offset * cpu-nr.





- arm,routable-irqs : Total number of gic irq inputs which are not directly

		  connected from the peripherals, but are routed dynamically

		  by a crossbar/multiplexer preceding the GIC. The GIC irq

		  input line is assigned dynamically when the corresponding

		  peripheral's crossbar line is mapped.

Example:

Example:





	intc: interrupt-controller@fff11000 {

	intc: interrupt-controller@fff11000 {
@@ -68,7 +63,6 @@ Example: 
		#interrupt-cells = <3>;

		#interrupt-cells = <3>;

		#address-cells = <1>;

		#address-cells = <1>;

		interrupt-controller;

		interrupt-controller;

		arm,routable-irqs = <160>;

		reg = <0xfff11000 0x1000>,

		reg = <0xfff11000 0x1000>,

		      <0xfff10100 0x100>;

		      <0xfff10100 0x100>;

	};

	};

Documentation/devicetree/bindings/arm/omap/crossbar.txt

+5 −13
Original line number Original line Diff line number Diff line
@@ -9,7 +9,9 @@ inputs. 
Required properties:

Required properties:

- compatible : Should be "ti,irq-crossbar"

- compatible : Should be "ti,irq-crossbar"

- reg: Base address and the size of the crossbar registers.

- reg: Base address and the size of the crossbar registers.

- ti,max-irqs: Total number of irqs available at the interrupt controller.

- interrupt-controller: indicates that this block is an interrupt controller.

- interrupt-parent: the interrupt controller this block is connected to.

- ti,max-irqs: Total number of irqs available at the parent interrupt controller.

- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.

- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.

- ti,reg-size: Size of a individual register in bytes. Every individual

- ti,reg-size: Size of a individual register in bytes. Every individual

	    register is assumed to be of same size. Valid sizes are 1, 2, 4.

	    register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties: 
  when the interrupt controller irq is unused (when not provided, default is 0)

  when the interrupt controller irq is unused (when not provided, default is 0)





Examples:

Examples:

		crossbar_mpu: @4a020000 {

		crossbar_mpu: crossbar@4a002a48 {

			compatible = "ti,irq-crossbar";

			compatible = "ti,irq-crossbar";

			reg = <0x4a002a48 0x130>;

			reg = <0x4a002a48 0x130>;

			ti,max-irqs = <160>;

			ti,max-irqs = <160>;

			ti,max-crossbar-sources = <400>;

			ti,max-crossbar-sources = <400>;

			ti,reg-size = <2>;

			ti,reg-size = <2>;

			ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;

			ti,irqs-reserved = <0 1 2 3 5 6 131 132>;

			ti,irqs-skip = <10 133 139 140>;

			ti,irqs-skip = <10 133 139 140>;

		};

		};
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further details. 




An interrupt consumer on an SoC using crossbar will use:

An interrupt consumer on an SoC using crossbar will use:

	interrupts = <GIC_SPI request_number interrupt_level>

	interrupts = <GIC_SPI request_number interrupt_level>

When the request number is between 0 to that described by

"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the

request_number is greater than "ti,max-crossbar-sources", then it is mapped as a

quirky hardware mapping direct to GIC.





Example:

Example:

	device_x@0x4a023000 {

	device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example: 
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

		...

		...

	};
 
	};
 


	device_y@0x4a033000 {

		/* Direct mapped GIC SPI 1 used */

		interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;

		...

	};

Documentation/devicetree/bindings/arm/samsung/pmu.txt

+17 −0
Original line number Original line Diff line number Diff line
@@ -29,10 +29,27 @@ Properties: 
 - clocks : list of phandles and specifiers to all input clocks listed in

 - clocks : list of phandles and specifiers to all input clocks listed in

		clock-names property.

		clock-names property.





Optional properties:



Some PMUs are capable of behaving as an interrupt controller (mostly

to wake up a suspended PMU). In which case, they can have the

following properties:



- interrupt-controller: indicate that said PMU is an interrupt controller



- #interrupt-cells: must be identical to the that of the parent interrupt

  controller.



- interrupt-parent: a phandle indicating which interrupt controller

  this PMU signals interrupts to.



Example :

Example :

pmu_system_controller: system-controller@10040000 {

pmu_system_controller: system-controller@10040000 {

	compatible = "samsung,exynos5250-pmu", "syscon";

	compatible = "samsung,exynos5250-pmu", "syscon";

	reg = <0x10040000 0x5000>;

	reg = <0x10040000 0x5000>;

	interrupt-controller;

	#interrupt-cells = <3>;

	interrupt-parent = <&gic>;

	#clock-cells = <1>;

	#clock-cells = <1>;

	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",

	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",

			"clkout4", "clkout8", "clkout9";

			"clkout4", "clkout8", "clkout9";

Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt

0 → 100644
+43 −0
Original line number Original line Diff line number Diff line 
NVIDIA Legacy Interrupt Controller



All Tegra SoCs contain a legacy interrupt controller that routes

interrupts to the GIC, and also serves as a wakeup source. It is also

referred to as "ictlr", hence the name of the binding.



The HW block exposes a number of interrupt controllers, each

implementing a set of 32 interrupts.



Required properties:



- compatible : should be: "nvidia,tegra<chip>-ictlr". The LIC on

  subsequent SoCs remained backwards-compatible with Tegra30, so on

  Tegra generations later than Tegra30 the compatible value should

  include "nvidia,tegra30-ictlr".	

- reg : Specifies base physical address and size of the registers.

  Each controller must be described separately (Tegra20 has 4 of them,

  whereas Tegra30 and later have 5"  

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value must be 3.

- interrupt-parent : a phandle to the GIC these interrupts are routed

  to.



Notes:



- Because this HW ultimately routes interrupts to the GIC, the

  interrupt specifier must be that of the GIC.

- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs

  are explicitly forbidden.



Example:



	ictlr: interrupt-controller@60004000 {

		compatible = "nvidia,tegra20-ictlr", "nvidia,tegra-ictlr";

		reg = <0x60004000 64>,

		      <0x60004100 64>,

		      <0x60004200 64>,

		      <0x60004300 64>;

		interrupt-controller;

		#interrupt-cells = <3>;

		interrupt-parent = <&intc>;

	};

Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu

0 → 100644
+33 −0
Original line number Original line Diff line number Diff line 
TI OMAP4 Wake-up Generator



All TI OMAP4/5 (and their derivatives) an interrupt controller that

routes interrupts to the GIC, and also serves as a wakeup source. It

is also referred to as "WUGEN-MPU", hence the name of the binding.



Reguired properties:



- compatible : should contain at least "ti,omap4-wugen-mpu" or

  "ti,omap5-wugen-mpu"

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value must be 3.

- interrupt-parent : a phandle to the GIC these interrupts are routed

  to.



Notes:



- Because this HW ultimately routes interrupts to the GIC, the

  interrupt specifier must be that of the GIC.

- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs

  are explicitly forbiden.



Example:



       wakeupgen: interrupt-controller@48281000 {

               compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";

               interrupt-controller;

               #interrupt-cells = <3>;

               reg = <0x48281000 0x1000>;

               interrupt-parent = <&gic>;

       };