drm/sun4i: Implement A83T HDMI driver (b7c7436a) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/gpu/drm/sun4i/Kconfig

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Original line number	Diff line number	Diff line
		@@ -40,6 +40,15 @@ config DRM_SUN4I_BACKEND
		do some alpha blending and feed graphics to TCON. If M is
		selected the module will be called sun4i-backend.

		config DRM_SUN8I_DW_HDMI
		tristate "Support for Allwinner version of DesignWare HDMI"
		depends on DRM_SUN4I
		select DRM_DW_HDMI
		help
		Choose this option if you have an Allwinner SoC with the
		DesignWare HDMI controller with custom HDMI PHY. If M is
		selected the module will be called sun8i_dw_hdmi.

		config DRM_SUN8I_MIXER
		tristate "Support for Allwinner Display Engine 2.0 Mixer"
		default MACH_SUN8I

drivers/gpu/drm/sun4i/Makefile

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Original line number	Diff line number	Diff line
		@@ -10,6 +10,9 @@ sun4i-drm-hdmi-y += sun4i_hdmi_enc.o
		sun4i-drm-hdmi-y += sun4i_hdmi_i2c.o
		sun4i-drm-hdmi-y += sun4i_hdmi_tmds_clk.o

		sun8i-drm-hdmi-y += sun8i_dw_hdmi.o
		sun8i-drm-hdmi-y += sun8i_hdmi_phy.o

		sun8i-mixer-y += sun8i_mixer.o sun8i_ui_layer.o \
		sun8i_vi_layer.o sun8i_ui_scaler.o \
		sun8i_vi_scaler.o sun8i_csc.o
		@@ -27,4 +30,5 @@ obj-$(CONFIG_DRM_SUN4I) += sun6i_drc.o

		obj-$(CONFIG_DRM_SUN4I_BACKEND) += sun4i-backend.o sun4i-frontend.o
		obj-$(CONFIG_DRM_SUN4I_HDMI) += sun4i-drm-hdmi.o
		obj-$(CONFIG_DRM_SUN8I_DW_HDMI) += sun8i-drm-hdmi.o
		obj-$(CONFIG_DRM_SUN8I_MIXER) += sun8i-mixer.o

drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c

0 → 100644

+196 −0

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0+
		/*
		* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
		*/

		#include <linux/component.h>
		#include <linux/module.h>
		#include <linux/platform_device.h>

		#include <drm/drm_of.h>
		#include <drm/drmP.h>
		#include <drm/drm_crtc_helper.h>

		#include "sun8i_dw_hdmi.h"

		static void sun8i_dw_hdmi_encoder_mode_set(struct drm_encoder *encoder,
		struct drm_display_mode *mode,
		struct drm_display_mode *adj_mode)
		{
		struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder);

		clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000);
		}

		static const struct drm_encoder_helper_funcs
		sun8i_dw_hdmi_encoder_helper_funcs = {
		.mode_set = sun8i_dw_hdmi_encoder_mode_set,
		};

		static const struct drm_encoder_funcs sun8i_dw_hdmi_encoder_funcs = {
		.destroy = drm_encoder_cleanup,
		};

		static enum drm_mode_status
		sun8i_dw_hdmi_mode_valid(struct drm_connector *connector,
		const struct drm_display_mode *mode)
		{
		if (mode->clock > 297000)
		return MODE_CLOCK_HIGH;

		return MODE_OK;
		}

		static int sun8i_dw_hdmi_bind(struct device dev, struct device master,
		void *data)
		{
		struct platform_device *pdev = to_platform_device(dev);
		struct dw_hdmi_plat_data *plat_data;
		struct drm_device *drm = data;
		struct device_node *phy_node;
		struct drm_encoder *encoder;
		struct sun8i_dw_hdmi *hdmi;
		int ret;

		if (!pdev->dev.of_node)
		return -ENODEV;

		hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
		if (!hdmi)
		return -ENOMEM;

		plat_data = &hdmi->plat_data;
		hdmi->dev = &pdev->dev;
		encoder = &hdmi->encoder;

		encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
		/*
		* If we failed to find the CRTC(s) which this encoder is
		* supposed to be connected to, it's because the CRTC has
		* not been registered yet. Defer probing, and hope that
		* the required CRTC is added later.
		*/
		if (encoder->possible_crtcs == 0)
		return -EPROBE_DEFER;

		hdmi->rst_ctrl = devm_reset_control_get(dev, "ctrl");
		if (IS_ERR(hdmi->rst_ctrl)) {
		dev_err(dev, "Could not get ctrl reset control\n");
		return PTR_ERR(hdmi->rst_ctrl);
		}

		hdmi->clk_tmds = devm_clk_get(dev, "tmds");
		if (IS_ERR(hdmi->clk_tmds)) {
		dev_err(dev, "Couldn't get the tmds clock\n");
		return PTR_ERR(hdmi->clk_tmds);
		}

		ret = reset_control_deassert(hdmi->rst_ctrl);
		if (ret) {
		dev_err(dev, "Could not deassert ctrl reset control\n");
		return ret;
		}

		ret = clk_prepare_enable(hdmi->clk_tmds);
		if (ret) {
		dev_err(dev, "Could not enable tmds clock\n");
		goto err_assert_ctrl_reset;
		}

		phy_node = of_parse_phandle(dev->of_node, "phys", 0);
		if (!phy_node) {
		dev_err(dev, "Can't found PHY phandle\n");
		goto err_disable_clk_tmds;
		}

		ret = sun8i_hdmi_phy_probe(hdmi, phy_node);
		of_node_put(phy_node);
		if (ret) {
		dev_err(dev, "Couldn't get the HDMI PHY\n");
		goto err_disable_clk_tmds;
		}

		drm_encoder_helper_add(encoder, &sun8i_dw_hdmi_encoder_helper_funcs);
		drm_encoder_init(drm, encoder, &sun8i_dw_hdmi_encoder_funcs,
		DRM_MODE_ENCODER_TMDS, NULL);

		sun8i_hdmi_phy_init(hdmi->phy);

		plat_data->mode_valid = &sun8i_dw_hdmi_mode_valid;
		plat_data->phy_ops = sun8i_hdmi_phy_get_ops();
		plat_data->phy_name = "sun8i_dw_hdmi_phy";
		plat_data->phy_data = hdmi->phy;

		platform_set_drvdata(pdev, hdmi);

		hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);

		/*
		* If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
		* which would have called the encoder cleanup. Do it manually.
		*/
		if (IS_ERR(hdmi->hdmi)) {
		ret = PTR_ERR(hdmi->hdmi);
		goto cleanup_encoder;
		}

		return 0;

		cleanup_encoder:
		drm_encoder_cleanup(encoder);
		sun8i_hdmi_phy_remove(hdmi);
		err_disable_clk_tmds:
		clk_disable_unprepare(hdmi->clk_tmds);
		err_assert_ctrl_reset:
		reset_control_assert(hdmi->rst_ctrl);

		return ret;
		}

		static void sun8i_dw_hdmi_unbind(struct device dev, struct device master,
		void *data)
		{
		struct sun8i_dw_hdmi *hdmi = dev_get_drvdata(dev);

		dw_hdmi_unbind(hdmi->hdmi);
		sun8i_hdmi_phy_remove(hdmi);
		clk_disable_unprepare(hdmi->clk_tmds);
		reset_control_assert(hdmi->rst_ctrl);
		}

		static const struct component_ops sun8i_dw_hdmi_ops = {
		.bind = sun8i_dw_hdmi_bind,
		.unbind = sun8i_dw_hdmi_unbind,
		};

		static int sun8i_dw_hdmi_probe(struct platform_device *pdev)
		{
		return component_add(&pdev->dev, &sun8i_dw_hdmi_ops);
		}

		static int sun8i_dw_hdmi_remove(struct platform_device *pdev)
		{
		component_del(&pdev->dev, &sun8i_dw_hdmi_ops);

		return 0;
		}

		static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = {
		{ .compatible = "allwinner,sun8i-a83t-dw-hdmi" },
		{ /* sentinel */ },
		};
		MODULE_DEVICE_TABLE(of, sun8i_dw_hdmi_dt_ids);

		struct platform_driver sun8i_dw_hdmi_pltfm_driver = {
		.probe = sun8i_dw_hdmi_probe,
		.remove = sun8i_dw_hdmi_remove,
		.driver = {
		.name = "sun8i-dw-hdmi",
		.of_match_table = sun8i_dw_hdmi_dt_ids,
		},
		};
		module_platform_driver(sun8i_dw_hdmi_pltfm_driver);

		MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
		MODULE_DESCRIPTION("Allwinner DW HDMI bridge");
		MODULE_LICENSE("GPL");

drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h

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		/* SPDX-License-Identifier: GPL-2.0+ */
		/*
		* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
		*/

		#ifndef _SUN8I_DW_HDMI_H_
		#define _SUN8I_DW_HDMI_H_

		#include <drm/bridge/dw_hdmi.h>
		#include <drm/drm_encoder.h>
		#include <linux/clk.h>
		#include <linux/regmap.h>
		#include <linux/reset.h>

		struct sun8i_hdmi_phy {
		struct clk *clk_bus;
		struct clk *clk_mod;
		struct regmap *regs;
		struct reset_control *rst_phy;
		};

		struct sun8i_dw_hdmi {
		struct clk *clk_tmds;
		struct device *dev;
		struct dw_hdmi *hdmi;
		struct drm_encoder encoder;
		struct sun8i_hdmi_phy *phy;
		struct dw_hdmi_plat_data plat_data;
		struct reset_control *rst_ctrl;
		};

		static inline struct sun8i_dw_hdmi *
		encoder_to_sun8i_dw_hdmi(struct drm_encoder *encoder)
		{
		return container_of(encoder, struct sun8i_dw_hdmi, encoder);
		}

		int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi hdmi, struct device_node node);
		void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi);

		void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
		const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void);

		#endif /* _SUN8I_DW_HDMI_H_ */

drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c

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+270 −0

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0+
		/*
		* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
		*/

		#include <linux/of_address.h>

		#include "sun8i_dw_hdmi.h"

		#define SUN8I_HDMI_PHY_DBG_CTRL_REG 0x0000
		#define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK BIT(0)
		#define SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK GENMASK(15, 8)
		#define SUN8I_HDMI_PHY_DBG_CTRL_POL(val) (val << 8)
		#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK GENMASK(23, 16)
		#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR(addr) (addr << 16)

		#define SUN8I_HDMI_PHY_REXT_CTRL_REG 0x0004
		#define SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN BIT(31)

		#define SUN8I_HDMI_PHY_READ_EN_REG 0x0010
		#define SUN8I_HDMI_PHY_READ_EN_MAGIC 0x54524545

		#define SUN8I_HDMI_PHY_UNSCRAMBLE_REG 0x0014
		#define SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC 0x42494E47

		/*
		* Address can be actually any value. Here is set to same value as
		* it is set in BSP driver.
		*/
		#define I2C_ADDR 0x69

		static int sun8i_hdmi_phy_config(struct dw_hdmi hdmi, void data,
		struct drm_display_mode *mode)
		{
		struct sun8i_hdmi_phy phy = (struct sun8i_hdmi_phy )data;
		u32 val = 0;

		if ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
		(mode->flags & DRM_MODE_FLAG_NHSYNC)) {
		val = 0x03;
		}

		regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
		SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK,
		SUN8I_HDMI_PHY_DBG_CTRL_POL(val));

		regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
		SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN,
		SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN);

		/* power down */
		dw_hdmi_phy_gen2_txpwron(hdmi, 0);
		dw_hdmi_phy_gen2_pddq(hdmi, 1);

		dw_hdmi_phy_reset(hdmi);

		dw_hdmi_phy_gen2_pddq(hdmi, 0);

		dw_hdmi_phy_i2c_set_addr(hdmi, I2C_ADDR);

		/*
		* Values are taken from BSP HDMI driver. Although AW didn't
		* release any documentation, explanation of this values can
		* be found in i.MX 6Dual/6Quad Reference Manual.
		*/
		if (mode->crtc_clock <= 27000) {
		dw_hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06);
		dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
		dw_hdmi_phy_i2c_write(hdmi, 0x08da, 0x10);
		dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);
		dw_hdmi_phy_i2c_write(hdmi, 0x0318, 0x0e);
		dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);
		} else if (mode->crtc_clock <= 74250) {
		dw_hdmi_phy_i2c_write(hdmi, 0x0540, 0x06);
		dw_hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
		dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
		dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);
		dw_hdmi_phy_i2c_write(hdmi, 0x02b5, 0x0e);
		dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);
		} else if (mode->crtc_clock <= 148500) {
		dw_hdmi_phy_i2c_write(hdmi, 0x04a0, 0x06);
		dw_hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
		dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
		dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);
		dw_hdmi_phy_i2c_write(hdmi, 0x0021, 0x0e);
		dw_hdmi_phy_i2c_write(hdmi, 0x8029, 0x09);
		} else {
		dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x06);
		dw_hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
		dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
		dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);
		dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x0e);
		dw_hdmi_phy_i2c_write(hdmi, 0x802b, 0x09);
		}

		dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x1e);
		dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);
		dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x17);

		dw_hdmi_phy_gen2_txpwron(hdmi, 1);

		return 0;
		};

		static void sun8i_hdmi_phy_disable(struct dw_hdmi hdmi, void data)
		{
		struct sun8i_hdmi_phy phy = (struct sun8i_hdmi_phy )data;

		dw_hdmi_phy_gen2_txpwron(hdmi, 0);
		dw_hdmi_phy_gen2_pddq(hdmi, 1);

		regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
		SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, 0);
		}

		static const struct dw_hdmi_phy_ops sun8i_hdmi_phy_ops = {
		.init = &sun8i_hdmi_phy_config,
		.disable = &sun8i_hdmi_phy_disable,
		.read_hpd = &dw_hdmi_phy_read_hpd,
		.update_hpd = &dw_hdmi_phy_update_hpd,
		.setup_hpd = &dw_hdmi_phy_setup_hpd,
		};

		void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy)
		{
		/* enable read access to HDMI controller */
		regmap_write(phy->regs, SUN8I_HDMI_PHY_READ_EN_REG,
		SUN8I_HDMI_PHY_READ_EN_MAGIC);

		/* unscramble register offsets */
		regmap_write(phy->regs, SUN8I_HDMI_PHY_UNSCRAMBLE_REG,
		SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC);

		regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
		SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK,
		SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK);

		/*
		* Set PHY I2C address. It must match to the address set by
		* dw_hdmi_phy_set_slave_addr().
		*/
		regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
		SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK,
		SUN8I_HDMI_PHY_DBG_CTRL_ADDR(I2C_ADDR));
		}

		const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void)
		{
		return &sun8i_hdmi_phy_ops;
		}

		static struct regmap_config sun8i_hdmi_phy_regmap_config = {
		.reg_bits = 32,
		.val_bits = 32,
		.reg_stride = 4,
		.max_register = SUN8I_HDMI_PHY_UNSCRAMBLE_REG,
		.name = "phy"
		};

		static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
		{ .compatible = "allwinner,sun8i-a83t-hdmi-phy" },
		{ /* sentinel */ }
		};

		int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi hdmi, struct device_node node)
		{
		struct device *dev = hdmi->dev;
		struct sun8i_hdmi_phy *phy;
		struct resource res;
		void __iomem *regs;
		int ret;

		if (!of_match_node(sun8i_hdmi_phy_of_table, node)) {
		dev_err(dev, "Incompatible HDMI PHY\n");
		return -EINVAL;
		}

		phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
		if (!phy)
		return -ENOMEM;

		ret = of_address_to_resource(node, 0, &res);
		if (ret) {
		dev_err(dev, "phy: Couldn't get our resources\n");
		return ret;
		}

		regs = devm_ioremap_resource(dev, &res);
		if (IS_ERR(regs)) {
		dev_err(dev, "Couldn't map the HDMI PHY registers\n");
		return PTR_ERR(regs);
		}

		phy->regs = devm_regmap_init_mmio(dev, regs,
		&sun8i_hdmi_phy_regmap_config);
		if (IS_ERR(phy->regs)) {
		dev_err(dev, "Couldn't create the HDMI PHY regmap\n");
		return PTR_ERR(phy->regs);
		}

		phy->clk_bus = of_clk_get_by_name(node, "bus");
		if (IS_ERR(phy->clk_bus)) {
		dev_err(dev, "Could not get bus clock\n");
		return PTR_ERR(phy->clk_bus);
		}

		phy->clk_mod = of_clk_get_by_name(node, "mod");
		if (IS_ERR(phy->clk_mod)) {
		dev_err(dev, "Could not get mod clock\n");
		ret = PTR_ERR(phy->clk_mod);
		goto err_put_clk_bus;
		}

		phy->rst_phy = of_reset_control_get_shared(node, "phy");
		if (IS_ERR(phy->rst_phy)) {
		dev_err(dev, "Could not get phy reset control\n");
		ret = PTR_ERR(phy->rst_phy);
		goto err_put_clk_mod;
		}

		ret = reset_control_deassert(phy->rst_phy);
		if (ret) {
		dev_err(dev, "Cannot deassert phy reset control: %d\n", ret);
		goto err_put_rst_phy;
		}

		ret = clk_prepare_enable(phy->clk_bus);
		if (ret) {
		dev_err(dev, "Cannot enable bus clock: %d\n", ret);
		goto err_deassert_rst_phy;
		}

		ret = clk_prepare_enable(phy->clk_mod);
		if (ret) {
		dev_err(dev, "Cannot enable mod clock: %d\n", ret);
		goto err_disable_clk_bus;
		}

		hdmi->phy = phy;

		return 0;

		err_disable_clk_bus:
		clk_disable_unprepare(phy->clk_bus);
		err_deassert_rst_phy:
		reset_control_assert(phy->rst_phy);
		err_put_rst_phy:
		reset_control_put(phy->rst_phy);
		err_put_clk_mod:
		clk_put(phy->clk_mod);
		err_put_clk_bus:
		clk_put(phy->clk_bus);

		return ret;
		}

		void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi)
		{
		struct sun8i_hdmi_phy *phy = hdmi->phy;

		clk_disable_unprepare(phy->clk_mod);
		clk_disable_unprepare(phy->clk_bus);

		reset_control_assert(phy->rst_phy);

		reset_control_put(phy->rst_phy);

		clk_put(phy->clk_mod);
		clk_put(phy->clk_bus);
		}