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Commit b7bbdaf1 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: add null pointer checks for parent clocks"

parents ca1d0418 758ccc70

drivers/clk/qcom/clk-alpha-pll.c

+8 −2
Original line number Diff line number Diff line
@@ -1195,6 +1195,7 @@ clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, 
				    unsigned long *prate)

{

	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);

	struct clk_hw *parent_hw;

	u32 ctl, div;



	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
@@ -1203,8 +1204,13 @@ clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, 
	ctl &= BIT(pll->width) - 1;

	div = 1 << fls(ctl);



	if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)

		*prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);

	if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {

		parent_hw = clk_hw_get_parent(hw);

		if (!parent_hw)

			return -EINVAL;



		*prate = clk_hw_round_rate(parent_hw, div * rate);

	}



	return DIV_ROUND_UP_ULL((u64)*prate, div);

}

drivers/clk/qcom/clk-rcg.c

+5 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013, The Linux Foundation. All rights reserved.

 * Copyright (c) 2013, 2019, The Linux Foundation. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and
@@ -422,6 +422,8 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, 


	clk_flags = clk_hw_get_flags(hw);

	p = clk_hw_get_parent_by_index(hw, index);

	if (!p)

		return -EINVAL;

	if (clk_flags & CLK_SET_RATE_PARENT) {

		rate = rate * f->pre_div;

		if (f->n) {
@@ -473,6 +475,8 @@ static int clk_rcg_bypass_determine_rate(struct clk_hw *hw, 
	int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src);



	req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index);

	if (!p)

		return -EINVAL;

	req->best_parent_rate = clk_hw_round_rate(p, req->rate);

	req->rate = req->best_parent_rate;

drivers/clk/qcom/clk-rcg2.c

+11 −0
Original line number Diff line number Diff line
@@ -761,6 +761,8 @@ static int clk_edp_pixel_determine_rate(struct clk_hw *hw, 


	/* Force the correct parent */

	req->best_parent_hw = clk_hw_get_parent_by_index(hw, index);

	if (!req->best_parent_hw)

		return -EINVAL;

	req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw);



	if (req->best_parent_rate == 810000000)
@@ -816,6 +818,8 @@ static int clk_byte_determine_rate(struct clk_hw *hw, 
		return -EINVAL;



	req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index);

	if (!p)

		return -EINVAL;

	req->best_parent_rate = parent_rate = clk_hw_round_rate(p, req->rate);



	div = DIV_ROUND_UP((2 * parent_rate), req->rate) - 1;
@@ -1115,6 +1119,8 @@ static int clk_gfx3d_determine_rate(struct clk_hw *hw, 
	int ret;



	xo = clk_hw_get_parent_by_index(hw, 0);

	if (!xo)

		return -EINVAL;

	if (req->rate == clk_hw_get_rate(xo)) {

		req->best_parent_hw = xo;

		return 0;
@@ -1123,6 +1129,8 @@ static int clk_gfx3d_determine_rate(struct clk_hw *hw, 
	p9 = clk_hw_get_parent_by_index(hw, 2);

	p2 = clk_hw_get_parent_by_index(hw, 3);

	p8 = clk_hw_get_parent_by_index(hw, 4);

	if (!p9 || !p2 || !p8)

		return -EINVAL;



	/* PLL9 is a fixed rate PLL */

	p9_rate = clk_hw_get_rate(p9);
@@ -1532,6 +1540,9 @@ static int clk_rcg2_dependent_set_parent(struct clk_hw *hw, u8 index) 
		return ret;



	p_hw = clk_hw_get_parent_by_index(rcg->clkr.dependent_hw, index);

	if (!p_hw)

		return -EINVAL;



	return clk_set_parent(rcg->clkr.dependent_hw->clk, p_hw->clk);

}