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Commit b76070b4 authored by Yaniv Rosner's avatar Yaniv Rosner Committed by David S. Miller
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bnx2x: Warpcore HW reset following fan failure 



Put Warpcore in low power mode in case of fan failure to reduce heat.

Signed-off-by: default avatarYaniv Rosner <yanivr@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 870516e1

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

+8 −0
Original line number Diff line number Diff line
@@ -8216,7 +8216,15 @@ static void bnx2x_warpcore_power_module(struct link_params *params, 
static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,

				    struct link_params *params)

{

	struct bnx2x *bp = params->bp;

	bnx2x_warpcore_power_module(params, phy, 0);

	/* Put Warpcore in low power mode */

	REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);



	/* Put LCPLL in low power mode */

	REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);

	REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);

	REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);

}



static void bnx2x_power_sfp_module(struct link_params *params,

drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h

+9 −0
Original line number Diff line number Diff line
@@ -1622,6 +1622,14 @@ 
   register bits. */

#define MISC_REG_LCPLL_CTRL_1					 0xa2a4

#define MISC_REG_LCPLL_CTRL_REG_2				 0xa2a8

/* [RW 1] LCPLL power down. Global register. Active High. Reset on POR

 * reset. */

#define MISC_REG_LCPLL_E40_PWRDWN				 0xaa74

/* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */

#define MISC_REG_LCPLL_E40_RESETB_ANA				 0xaa78

/* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR

 * reset. */

#define MISC_REG_LCPLL_E40_RESETB_DIG				 0xaa7c

/* [RW 4] Interrupt mask register #0 read/write */

#define MISC_REG_MISC_INT_MASK					 0xa388

/* [RW 1] Parity mask register #0 read/write */
@@ -1757,6 +1765,7 @@ 
 * is compared to the value on ctrl_md_devad. Drives output

 * misc_xgxs0_phy_addr. Global register. */

#define MISC_REG_WC0_CTRL_PHY_ADDR				 0xa9cc

#define MISC_REG_WC0_RESET					 0xac30

/* [RW 2] XMAC Core port mode. Indicates the number of ports on the system

   side. This should be less than or equal to phy_port_mode; if some of the

   ports are not used. This enables reduction of frequency on the core side.