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Commit b726e493 authored by Francois Romieu's avatar Francois Romieu
Browse files

r8169: sync existing 8168 device hardware start sequences with vendor driver 



This part of the driver should be reasonably in line with Realtek's
8.006.00 driver.

I have left some bits related to jumbo frame and optional features
aside for now.

Signed-off-by: default avatarFrancois Romieu <romieu@fr.zoreil.com>
Cc: Edward Hsu <edward_hsu@realtek.com.tw>
parent 2e68ae44

drivers/net/r8169.c

+75 −0
Original line number Diff line number Diff line
@@ -2384,8 +2384,38 @@ static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len) 
	}

}



static void rtl_disable_clock_request(struct pci_dev *pdev)

{

	struct net_device *dev = pci_get_drvdata(pdev);

	struct rtl8169_private *tp = netdev_priv(dev);

	int cap = tp->pcie_cap;



	if (cap) {

		u16 ctl;



		pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);

		ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;

		pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);

	}

}



#define R8168_CPCMD_QUIRK_MASK (\

	EnableBist | \

	Mac_dbgo_oe | \

	Force_half_dup | \

	Force_rxflow_en | \

	Force_txflow_en | \

	Cxpl_dbg_sel | \

	ASF | \

	PktCntrDisable | \

	Mac_dbgo_sel)



static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)

{

	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);



	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);



	rtl_tx_performance_tweak(pdev,

		(0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);

}
@@ -2393,25 +2423,70 @@ static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) 
static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)

{

	rtl_hw_start_8168bb(ioaddr, pdev);



	RTL_W8(EarlyTxThres, EarlyTxThld);



	RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));

}



static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)

{

	RTL_W8(Config1, RTL_R8(Config1) | Speed_down);



	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);



	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);



	rtl_disable_clock_request(pdev);



	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);

}



static void rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)

{

	static struct ephy_info e_info_8168cp[] = {

		{ 0x01, 0,	0x0001 },

		{ 0x02, 0x0800,	0x1000 },

		{ 0x03, 0,	0x0042 },

		{ 0x06, 0x0080,	0x0000 },

		{ 0x07, 0,	0x2000 }

	};



	rtl_csi_access_enable(ioaddr);



	rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));



	__rtl_hw_start_8168cp(ioaddr, pdev);

}



static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)

{

	static struct ephy_info e_info_8168c_1[] = {

		{ 0x02, 0x0800,	0x1000 },

		{ 0x03, 0,	0x0002 },

		{ 0x06, 0x0080,	0x0000 }

	};



	rtl_csi_access_enable(ioaddr);



	RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);



	rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));



	__rtl_hw_start_8168cp(ioaddr, pdev);

}



static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)

{

	static struct ephy_info e_info_8168c_2[] = {

		{ 0x01, 0,	0x0001 },

		{ 0x03, 0x0400,	0x0220 }

	};



	rtl_csi_access_enable(ioaddr);



	rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));



	__rtl_hw_start_8168cp(ioaddr, pdev);

}