Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b703df6f authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller
Browse files

tg3: Add 57765 asic rev 



This patch adds the 57765 asic revision.

Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 19cfaecc

drivers/net/tg3.c

+53 −19
Original line number Diff line number Diff line
@@ -5514,7 +5514,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, 
	tnapi->tx_buffers[entry].skb = skb;

	pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&

	if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&

	    !mss && skb->len > ETH_DATA_LEN)

		base_flags |= TXD_FLAG_JMB_PKT;
@@ -5726,7 +5726,7 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb, 
			       (vlan_tx_tag_get(skb) << 16));

#endif



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&

	if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&

	    !mss && skb->len > ETH_DATA_LEN)

		base_flags |= TXD_FLAG_JMB_PKT;
@@ -6971,7 +6971,8 @@ static int tg3_chip_reset(struct tg3 *tp) 
	if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&

	    tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&

	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&

	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {

	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&

	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {

		val = tr32(0x7c00);



		tw32(0x7c00, val | (1 << 25));
@@ -7398,6 +7399,8 @@ static void tg3_rings_reset(struct tg3 *tp) 
	/* Disable all transmit rings but the first. */

	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))

		limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;

	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)

		limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;

	else

		limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
@@ -7412,7 +7415,8 @@ static void tg3_rings_reset(struct tg3 *tp) 
		limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;

	else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))

		limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;

	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)

	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||

		 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)

		limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;

	else

		limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
@@ -7609,7 +7613,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) 
	if (err)

		return err;



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {

		val = tr32(TG3PCI_DMA_RW_CTRL) &

		      ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;

		tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
@@ -7770,7 +7775,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) 
			     BDINFO_FLAGS_DISABLED);

		}



		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)

		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||

		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)

			val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |

			      (RX_STD_MAX_SIZE << 2);

		else
@@ -7787,7 +7793,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) 
			  tp->rx_jumbo_pending : 0;

	tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {

		tw32(STD_REPLENISH_LWM, 32);

		tw32(JMB_REPLENISH_LWM, 16);

	}
@@ -8464,7 +8471,8 @@ static int tg3_test_interrupt(struct tg3 *tp) 
	 * Turn off MSI one shot mode.  Otherwise this test has no

	 * observable way to know whether the interrupt was delivered.

	 */

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&

	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||

	     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&

	    (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {

		val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;

		tw32(MSGINT_MODE, val);
@@ -8507,7 +8515,8 @@ static int tg3_test_interrupt(struct tg3 *tp) 


	if (intr_ok) {

		/* Reenable MSI one shot mode. */

		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&

		if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||

		     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&

		    (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {

			val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;

			tw32(MSGINT_MODE, val);
@@ -8803,6 +8812,7 @@ static int tg3_open(struct net_device *dev) 
		}



		if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&

		    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&

		    (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&

		    (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {

			u32 val = tr32(PCIE_TRANSACTION_CFG);
@@ -11697,7 +11707,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp) 
			tg3_get_5761_nvram_info(tp);

		else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)

			tg3_get_5906_nvram_info(tp);

		else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)

		else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||

			 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)

			tg3_get_57780_nvram_info(tp);

		else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)

			tg3_get_5717_nvram_info(tp);
@@ -12531,6 +12542,8 @@ static void __devinit tg3_read_partno(struct tg3 *tp) 
	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&

		 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)

		strcpy(tp->board_part_number, "BCM57788");

	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)

		strcpy(tp->board_part_number, "BCM57765");

	else

		strcpy(tp->board_part_number, "none");

}
@@ -12820,6 +12833,15 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
			pci_read_config_dword(tp->pdev,

					      TG3PCI_GEN2_PRODID_ASICREV,

					      &prod_id_asic_rev);

		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||

			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||

			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||

			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||

			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||

			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)

			pci_read_config_dword(tp->pdev,

					      TG3PCI_GEN15_PRODID_ASICREV,

					      &prod_id_asic_rev);

		else

			pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,

					      &prod_id_asic_rev);
@@ -12973,7 +12995,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)

		tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
@@ -13000,7 +13023,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
	}



	/* Determine TSO capabilities */

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)

		tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;

	else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||

		 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
@@ -13036,7 +13060,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
			tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;

		}



		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {

		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||

		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {

			tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;

			tp->irq_max = TG3_IRQ_MAX_VECS;

		}
@@ -13050,9 +13075,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
		tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;

	}



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)

		tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;



	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||

	     (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)

		 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))

		tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;



	pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
@@ -13245,7 +13274,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)

		tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;



	/* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
@@ -13324,7 +13354,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
	    !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&

	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&

	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&

	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {

	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&

	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {

		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||

		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||

		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
@@ -13648,7 +13679,8 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) 
#endif

#endif



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {

		val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;

		goto out;

	}
@@ -13860,7 +13892,8 @@ static int __devinit tg3_test_dma(struct tg3 *tp) 


	tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)

		goto out;



	if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
@@ -14053,7 +14086,8 @@ static void __devinit tg3_init_link_config(struct tg3 *tp) 
static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)

{

	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&

	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {

	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&

	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {

		tp->bufmgr_config.mbuf_read_dma_low_water =

			DEFAULT_MB_RDMA_LOW_WATER_5705;

		tp->bufmgr_config.mbuf_mac_rx_low_water =

drivers/net/tg3.h

+9 −0
Original line number Diff line number Diff line
@@ -49,6 +49,12 @@ 
#define  TG3PCI_DEVICE_TIGON3_5717	 0x1655

#define  TG3PCI_DEVICE_TIGON3_5718	 0x1656

#define  TG3PCI_DEVICE_TIGON3_5724	 0x165c

#define  TG3PCI_DEVICE_TIGON3_57781	 0x16b1

#define  TG3PCI_DEVICE_TIGON3_57785	 0x16b5

#define  TG3PCI_DEVICE_TIGON3_57761	 0x16b0

#define  TG3PCI_DEVICE_TIGON3_57765	 0x16b4

#define  TG3PCI_DEVICE_TIGON3_57791	 0x16b2

#define  TG3PCI_DEVICE_TIGON3_57795	 0x16b6

/* 0x04 --> 0x64 unused */

#define TG3PCI_MSI_DATA			0x00000064

/* 0x66 --> 0x68 unused */
@@ -122,6 +128,7 @@ 
#define   ASIC_REV_5785			 0x5785

#define   ASIC_REV_57780		 0x57780

#define   ASIC_REV_5717			 0x5717

#define   ASIC_REV_57765		 0x57785

#define  GET_CHIP_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 8)

#define   CHIPREV_5700_AX		 0x70

#define   CHIPREV_5700_BX		 0x71
@@ -220,6 +227,7 @@ 
/* 0xc0 --> 0xf4 unused */



#define TG3PCI_GEN2_PRODID_ASICREV	0x000000f4

#define TG3PCI_GEN15_PRODID_ASICREV	0x000000fc

/* 0xf8 --> 0x200 unused */



#define TG3_CORR_ERR_STAT		0x00000110
@@ -2795,6 +2803,7 @@ struct tg3 { 
#define TG3_FLG3_4G_DMA_BNDRY_BUG	0x00080000

#define TG3_FLG3_40BIT_DMA_LIMIT_BUG	0x00100000

#define TG3_FLG3_SHORT_DMA_BUG		0x00200000

#define TG3_FLG3_USE_JUMBO_BDFLAG	0x00400000



	struct timer_list		timer;

	u16				timer_counter;