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Commit b6c58b1d authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: Improved multi-resource handling for SH7780 PCI. 



The SH7780 PCI controller supports 3 different ranges of PCI memory in
addition to its PCI I/O window. In the case of 29-bit mode, only 2 memory
windows are supported, while in 32-bit mode all 3 are visible. This
attempts to make the resource handling completely dynamic and to permit
platforms to map in as many apertures as they can handle.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent ef407bee

arch/sh/drivers/pci/fixups-dreamcast.c

+1 −1
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ static void __init gapspci_fixup_resources(struct pci_dev *dev) 
		/*

		 * We also assume that dev->devfn == 0

		 */

		dev->resource[1].start	= p->io_resource->start  + 0x100;

		dev->resource[1].start	= p->resources[0].start  + 0x100;

		dev->resource[1].end	= dev->resource[1].start + 0x200 - 1;



		/*

arch/sh/drivers/pci/fixups-se7751.c

+3 −3
Original line number Diff line number Diff line
@@ -97,12 +97,12 @@ int pci_fixup_pcic(struct pci_channel *chan) 
	* meaning all calls go straight through... use BUG_ON to

	* catch erroneous assumption.

	*/

	BUG_ON(chan->mem_resource->start != SH7751_PCI_MEMORY_BASE);

	BUG_ON(chan->resources[1].start != SH7751_PCI_MEMORY_BASE);



	PCIC_WRITE(SH7751_PCIMBR, chan->mem_resource->start);

	PCIC_WRITE(SH7751_PCIMBR, chan->resources[1].start);



	/* Set IOBR for window containing area specified in pci.h */

	PCIC_WRITE(SH7751_PCIIOBR, (chan->io_resource->start & SH7751_PCIIOBR_MASK));

	PCIC_WRITE(SH7751_PCIIOBR, (chan->resources[0].start & SH7751_PCIIOBR_MASK));



	/* All done, may as well say so... */

	printk("SH7751 PCI: Finished initialization of the PCI controller\n");

arch/sh/drivers/pci/pci-dreamcast.c

+14 −14
Original line number Diff line number Diff line
@@ -25,25 +25,25 @@ 
#include <asm/irq.h>

#include <mach/pci.h>



static struct resource gapspci_io_resource = {

static struct resource gapspci_resources[] = {

	{

		.name	= "GAPSPCI IO",

		.start	= GAPSPCI_BBA_CONFIG,

		.end	= GAPSPCI_BBA_CONFIG + GAPSPCI_BBA_CONFIG_SIZE - 1,

		.flags	= IORESOURCE_IO,

};



static struct resource gapspci_mem_resource = {

	},  {

		.name	= "GAPSPCI mem",

		.start	= GAPSPCI_DMA_BASE,

		.end	= GAPSPCI_DMA_BASE + GAPSPCI_DMA_SIZE - 1,

		.flags	= IORESOURCE_MEM,

	},

};



static struct pci_channel dreamcast_pci_controller = {

	.pci_ops	= &gapspci_pci_ops,

	.io_resource	= &gapspci_io_resource,

	.resources	= gapspci_resources,

	.nr_resources	= ARRAY_SIZE(gapspci_resources),

	.io_offset	= 0x00000000,

	.mem_resource	= &gapspci_mem_resource,

	.mem_offset	= 0x00000000,

};

arch/sh/drivers/pci/pci-sh5.c

+7 −8
Original line number Diff line number Diff line
@@ -89,14 +89,13 @@ static irqreturn_t pcish5_serr_irq(int irq, void *dev_id) 
	return IRQ_NONE;

}



static struct resource sh5_io_resource = { /* place holder */ };

static struct resource sh5_mem_resource = { /* place holder */ };

static struct resource sh5_pci_resources[2];



static struct pci_channel sh5pci_controller = {

	.pci_ops		= &sh5_pci_ops,

	.mem_resource		= &sh5_mem_resource,

	.resources		= sh5_pci_resources,

	.nr_resources		= ARRAY_SIZE(sh5_pci_resources),

	.mem_offset		= 0x00000000,

	.io_resource		= &sh5_io_resource,

	.io_offset		= 0x00000000,

};
@@ -210,11 +209,11 @@ static int __init sh5pci_init(void) 
        SH5PCI_WRITE(AINTM, ~0);

        SH5PCI_WRITE(PINTM, ~0);



	sh5_io_resource.start = PCI_IO_AREA;

	sh5_io_resource.end = PCI_IO_AREA + 0x10000;

	sh5_pci_resources[0].start = PCI_IO_AREA;

	sh5_pci_resources[0].end = PCI_IO_AREA + 0x10000;



	sh5_mem_resource.start = memStart;

	sh5_mem_resource.end = memStart + memSize;

	sh5_pci_resources[1].start = memStart;

	sh5_pci_resources[1].end = memStart + memSize;



	return register_pci_controller(&sh5pci_controller);

}

arch/sh/drivers/pci/pci-sh7751.c

+16 −16
Original line number Diff line number Diff line
@@ -44,25 +44,25 @@ static int __init __area_sdram_check(struct pci_channel *chan, 
	return 1;

}



static struct resource sh7751_io_resource = {

static struct resource sh7751_pci_resources[] = {

	{

		.name	= "SH7751_IO",

		.start	= SH7751_PCI_IO_BASE,

		.end	= SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,

		.flags	= IORESOURCE_IO

};



static struct resource sh7751_mem_resource = {

	}, {

		.name	= "SH7751_mem",

		.start	= SH7751_PCI_MEMORY_BASE,

		.end	= SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,

		.flags	= IORESOURCE_MEM

	},

};



static struct pci_channel sh7751_pci_controller = {

	.pci_ops	= &sh4_pci_ops,

	.mem_resource	= &sh7751_mem_resource,

	.resources	= sh7751_pci_resources,

	.nr_resources	= ARRAY_SIZE(sh7751_pci_resources),

	.mem_offset	= 0x00000000,

	.io_resource	= &sh7751_io_resource,

	.io_offset	= 0x00000000,

	.io_map_base	= SH7751_PCI_IO_BASE,

};
@@ -128,13 +128,13 @@ static int __init sh7751_pci_init(void) 
	/* Set the local 16MB PCI memory space window to

	 * the lowest PCI mapped address

	 */

	word = chan->mem_resource->start & SH4_PCIMBR_MASK;

	word = chan->resources[1].start & SH4_PCIMBR_MASK;

	pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);

	pci_write_reg(chan, word , SH4_PCIMBR);



	/* Make sure the MSB's of IO window are set to access PCI space

	 * correctly */

	word = chan->io_resource->start & SH4_PCIIOBR_MASK;

	word = chan->resources[0].start & SH4_PCIIOBR_MASK;

	pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);

	pci_write_reg(chan, word, SH4_PCIIOBR);