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Commit b6ae7a26 authored by Pritesh Raithatha's avatar Pritesh Raithatha Committed by Linus Walleij
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pinctrl: tegra114: add pinctrl driver for NVIDIA's Tegra114 SoC 



This adds a driver for the Tegra114 pinmux, and required
parameterization data for Tegra114.

The driver uses the common Tegra pincontrol driver utility
functions to implement the majority of the driver.

This driver is not compatible with the earlier NVIDIA's SoCs,
hence add new compatibile as "nvidia,tegra114-pinmux".

Originally written by Pritesh.
ldewangan:
	- cleanup the patches,
	- remove non-require tables.
	- Use module_platform_driver() for driver registartion.

Signed-off-by: default avatarPritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: default avatarLaxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 348d1bf7

Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt

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NVIDIA Tegra114 pinmux controller



The Tegra114 pinctrl binding is very similar to the Tegra20 and Tegra30

pinctrl binding, as described in nvidia,tegra20-pinmux.txt and

nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as

a baseline, and only documents the differences between the two bindings.



Required properties:

- compatible: "nvidia,tegra114-pinmux"

- reg: Should contain the register physical address and length for each of

  the pad control and mux registers. The first bank of address must be the

  driver strength pad control register address and second bank address must

  be pinmux register address.



Tegra114 adds the following optional properties for pin configuration subnodes:

- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.

- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.

- nvidia,lock: Integer. Lock the pin configuration against further changes

    until reset. 0: no, 1: yes.

- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.

- nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high.

- nvidia,drive-type: Integer. Valid range 0...3.



As with Tegra20 and Terga30, see the Tegra TRM for complete details regarding

which groups support which functionality.



Valid values for pin and group names are:



  per-pin mux groups:



    These all support nvidia,function, nvidia,tristate, nvidia,pull,

    nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,

    nvidia,io-reset and nvidia,rcv-sel.



    ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4,

    ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0,

    ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0,

    dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,

    sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6,

    sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4,

    ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,

    uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1,

    uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_sda_pc5,

    gen1_i2c_scl_pc4, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7,

    clk3_out_pee0, clk3_req_pee1, gmi_wp_n_pc7, gmi_iordy_pi5, gmi_wait_pi7,

    gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs0_n_pj0, gmi_cs1_n_pj2, gmi_cs2_n_pk3,

    gmi_cs3_n_pk4, gmi_cs4_n_pk2, gmi_cs6_n_pi3, gmi_cs7_n_pi6, gmi_ad0_pg0,

    gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,

    gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,

    gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,

    gmi_a16_pj7, gmi_a17_pb0, gmi_a18_pb1, gmi_a19_pk7, gmi_wr_n_pi0,

    gmi_oe_n_pi1, gmi_dqs_p_pj3, gmi_rst_n_pi4, gen2_i2c_scl_pt5,

    gen2_i2c_sda_pt6, sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,

    sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,

    sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, cam_mclk_pcc0,

    pcc1, pbb0, cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,

    pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1,

    kb_row2_pr2, kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6,

    kb_row7_pr7, kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_col0_pq0,

    kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,

    kb_col6_pq6, kb_col7_pq7, clk_32k_out_pa0, sys_clk_req_pz5, core_pwr_req,

    cpu_pwr_req, pwr_int_n, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2,

    dap1_sclk_pn3, clk1_req_pee2, clk1_out_pw4, spdif_in_pk6, spdif_out_pk5,

    dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,

    gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, gpio_x4_aud_px4,

    gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7, sdmmc3_clk_pa6,

    sdmmc3_cmd_pa7, sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,

    sdmmc3_dat3_pb4, hdmi_cec_pee3, sdmmc1_wp_n_pv3, sdmmc3_cd_n_pv2,

    gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4, usb_vbus_en1_pn5,

    sdmmc3_clk_lb_in_pee5, sdmmc3_clk_lb_out_pee4, reset_out_n.



  drive groups:



    These all support nvidia,pull-down-strength, nvidia,pull-up-strength,

    nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all

    support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode

    and nvidia,drive-type.



    ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, dap1, dap2, dap3, dap4,

    dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,

    gmh, owr, uda.



Example:



	pinmux: pinmux {

		compatible = "nvidia,tegra114-pinmux";

		reg = <0x70000868 0x148		/* Pad control registers */

		       0x70003000 0x40c>;	/* PinMux registers */

	};



Example board file extract:



	pinctrl {

		sdmmc4_default: pinmux {

			sdmmc4_clk_pcc4 {

				nvidia,pins = "sdmmc4_clk_pcc4",

				nvidia,function = "sdmmc4";

				nvidia,pull = <0>;

				nvidia,tristate = <0>;

			};

			sdmmc4_dat0_paa0 {

				nvidia,pins = "sdmmc4_dat0_paa0",

						"sdmmc4_dat1_paa1",

						"sdmmc4_dat2_paa2",

						"sdmmc4_dat3_paa3",

						"sdmmc4_dat4_paa4",

						"sdmmc4_dat5_paa5",

						"sdmmc4_dat6_paa6",

						"sdmmc4_dat7_paa7";

				nvidia,function = "sdmmc4";

				nvidia,pull = <2>;

				nvidia,tristate = <0>;

			};

		};

	};



	sdhci@78000400 {

		pinctrl-names = "default";

		pinctrl-0 = <&sdmmc4_default>;

	};

drivers/pinctrl/Kconfig

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@@ -164,6 +164,10 @@ config PINCTRL_TEGRA30 
	bool

	bool

	select PINCTRL_TEGRA

	select PINCTRL_TEGRA





config PINCTRL_TEGRA114

	bool

	select PINCTRL_TEGRA



config PINCTRL_U300

config PINCTRL_U300

	bool "U300 pin controller driver"

	bool "U300 pin controller driver"

	depends on ARCH_U300

	depends on ARCH_U300

drivers/pinctrl/Makefile

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@@ -33,6 +33,7 @@ obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o 
obj-$(CONFIG_PINCTRL_TEGRA)	+= pinctrl-tegra.o

obj-$(CONFIG_PINCTRL_TEGRA)	+= pinctrl-tegra.o

obj-$(CONFIG_PINCTRL_TEGRA20)	+= pinctrl-tegra20.o

obj-$(CONFIG_PINCTRL_TEGRA20)	+= pinctrl-tegra20.o

obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o

obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o

obj-$(CONFIG_PINCTRL_TEGRA114)	+= pinctrl-tegra114.o

obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o

obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o

obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o

obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o

obj-$(CONFIG_PINCTRL_SAMSUNG)	+= pinctrl-samsung.o

obj-$(CONFIG_PINCTRL_SAMSUNG)	+= pinctrl-samsung.o

drivers/pinctrl/pinctrl-tegra114.c

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