Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

The arm64 port of the Linux kernel provides infrastructure to support

emulation of instructions which have been deprecated, or obsoleted in

the architecture. The infrastructure code uses undefined instruction

hooks to support emulation. Where available it also allows turning on

the instruction execution in hardware.

The emulation mode can be controlled by writing to sysctl nodes

(/proc/sys/abi). The following explains the different execution

behaviours and the corresponding values of the sysctl nodes -

* Undef

  Value: 0

  Generates undefined instruction abort. Default for instructions that

  have been obsoleted in the architecture, e.g., SWP

* Emulate

  Value: 1

  Uses software emulation. To aid migration of software, in this mode

  usage of emulated instruction is traced as well as rate limited

  warnings are issued. This is the default for deprecated

  instructions, .e.g., CP15 barriers

* Hardware Execution

  Value: 2

  Although marked as deprecated, some implementations may support the

  enabling/disabling of hardware support for the execution of these

  instructions. Using hardware execution generally provides better

  performance, but at the loss of ability to gather runtime statistics

  about the use of the deprecated instructions.

The default mode depends on the status of the instruction in the

architecture. Deprecated instructions should default to emulation

while obsolete instructions must be undefined by default.

Supported legacy instructions

-----------------------------

* SWP{B}

Node: /proc/sys/abi/swp

Status: Obsolete

Default: Undef (0)

* CP15 Barriers

Node: /proc/sys/abi/cp15_barrier

Status: Deprecated

Default: Emulate (1)

	select GENERIC_TIME_VSYSCALL

	select HANDLE_DOMAIN_IRQ

	select HARDIRQS_SW_RESEND

	select HAVE_ALIGNED_STRUCT_PAGE if SLUB

	select HAVE_ARCH_AUDITSYSCALL

	select HAVE_ARCH_JUMP_LABEL

	select HAVE_ARCH_KGDB

	select HAVE_ARCH_SECCOMP_FILTER

	select HAVE_ARCH_TRACEHOOK

	select HAVE_BPF_JIT

	select HAVE_C_RECORDMCOUNT

	select HAVE_CC_STACKPROTECTOR

	select HAVE_CMPXCHG_DOUBLE

	select HAVE_DEBUG_BUGVERBOSE

	select HAVE_DEBUG_KMEMLEAK

	select HAVE_DMA_API_DEBUG

menu "Kernel Features"

menu "ARM errata workarounds via the alternatives framework"

config ARM64_ERRATUM_826319

	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"

	default y

	help

	  This option adds an alternative code sequence to work around ARM

	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or

	  AXI master interface and an L2 cache.

	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors

	  and is unable to accept a certain write via this interface, it will

	  not progress on read data presented on the read data channel and the

	  system can deadlock.

	  The workaround promotes data cache clean instructions to

	  data cache clean-and-invalidate.

	  Please note that this does not necessarily enable the workaround,

	  as it depends on the alternative framework, which will only patch

	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_827319

	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"

	default y

	help

	  This option adds an alternative code sequence to work around ARM

	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI

	  master interface and an L2 cache.

	  Under certain conditions this erratum can cause a clean line eviction

	  to occur at the same time as another transaction to the same address

	  on the AMBA 5 CHI interface, which can cause data corruption if the

	  interconnect reorders the two transactions.

	  The workaround promotes data cache clean instructions to

	  data cache clean-and-invalidate.

	  Please note that this does not necessarily enable the workaround,

	  as it depends on the alternative framework, which will only patch

	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_824069

	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"

	default y

	help

	  This option adds an alternative code sequence to work around ARM

	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected

	  to a coherent interconnect.

	  If a Cortex-A53 processor is executing a store or prefetch for

	  write instruction at the same time as a processor in another

	  cluster is executing a cache maintenance operation to the same

	  address, then this erratum might cause a clean cache line to be

	  incorrectly marked as dirty.

	  The workaround promotes data cache clean instructions to

	  data cache clean-and-invalidate.

	  Please note that this option does not necessarily enable the

	  workaround, as it depends on the alternative framework, which will

	  only patch the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_819472

	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"

	default y

	help

	  This option adds an alternative code sequence to work around ARM

	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache

	  present when it is connected to a coherent interconnect.

	  If the processor is executing a load and store exclusive sequence at

	  the same time as a processor in another cluster is executing a cache

	  maintenance operation to the same address, then this erratum might

	  cause data corruption.

	  The workaround promotes data cache clean instructions to

	  data cache clean-and-invalidate.

	  Please note that this does not necessarily enable the workaround,

	  as it depends on the alternative framework, which will only patch

	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_832075

	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"

	default y

	help

	  This option adds an alternative code sequence to work around ARM

	  erratum 832075 on Cortex-A57 parts up to r1p2.

	  Affected Cortex-A57 parts might deadlock when exclusive load/store

	  instructions to Write-Back memory are mixed with Device loads.

	  The workaround is to promote device loads to use Load-Acquire

	  semantics.

	  Please note that this does not necessarily enable the workaround,

	  as it depends on the alternative framework, which will only patch

	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

endmenu

choice

	prompt "Page size"

	default ARM64_4K_PAGES

source "mm/Kconfig"

config SECCOMP

	bool "Enable seccomp to safely compute untrusted bytecode"

	---help---

	  This kernel feature is useful for number crunching applications

	  that may need to compute untrusted bytecode during their

	  execution. By using pipes or other transports made available to

	  the process as file descriptors supporting the read/write

	  syscalls, it's possible to isolate those applications in

	  their own address space using seccomp. Once seccomp is

	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled

	  and the task is only allowed to execute a few safe syscalls

	  defined by each seccomp mode.

config XEN_DOM0

	def_bool y

	depends on XEN

	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)

	default "11"

menuconfig ARMV8_DEPRECATED

	bool "Emulate deprecated/obsolete ARMv8 instructions"

	depends on COMPAT

	help

	  Legacy software support may require certain instructions

	  that have been deprecated or obsoleted in the architecture.

	  Enable this config to enable selective emulation of these

	  features.

	  If unsure, say Y

if ARMV8_DEPRECATED

config SWP_EMULATION

	bool "Emulate SWP/SWPB instructions"

	help

	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that

	  they are always undefined. Say Y here to enable software

	  emulation of these instructions for userspace using LDXR/STXR.

	  In some older versions of glibc [<=2.8] SWP is used during futex

	  trylock() operations with the assumption that the code will not

	  be preempted. This invalid assumption may be more likely to fail

	  with SWP emulation enabled, leading to deadlock of the user

	  application.

	  NOTE: when accessing uncached shared regions, LDXR/STXR rely

	  on an external transaction monitoring block called a global

	  monitor to maintain update atomicity. If your system does not

	  implement a global monitor, this option can cause programs that

	  perform SWP operations to uncached memory to deadlock.

	  If unsure, say Y

config CP15_BARRIER_EMULATION

	bool "Emulate CP15 Barrier instructions"

	help

	  The CP15 barrier instructions - CP15ISB, CP15DSB, and

	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is

	  strongly recommended to use the ISB, DSB, and DMB

	  instructions instead.

	  Say Y here to enable software emulation of these

	  instructions for AArch32 userspace code. When this option is

	  enabled, CP15 barrier usage is traced which can help

	  identify software that needs updating.

	  If unsure, say Y

endif

endmenu

menu "Boot options"

	  allow the kernel to be booted as an EFI application. This

	  is only useful on systems that have UEFI firmware.

config DMI

	bool "Enable support for SMBIOS (DMI) tables"

	depends on EFI

	default y

	help

	  This enables SMBIOS/DMI feature for systems.

	  This option is only useful on systems that have UEFI firmware.

	  However, even with this option, the resultant kernel should

	  continue to boot on existing non-UEFI platforms.

endmenu

menu "Userspace binary formats"

	bool

	default y

config ARM64_PTDUMP

	bool "Export kernel pagetable layout to userspace via debugfs"

	depends on DEBUG_KERNEL

	select DEBUG_FS

        help

	  Say Y here if you want to show the kernel pagetable layout in a

	  debugfs file. This information is only useful for kernel developers

	  who are working in architecture specific areas of the kernel.

	  It is probably not a good idea to enable this feature in a production

	  kernel.

	  If in doubt, say "N"

config STRICT_DEVMEM

	bool "Filter access to /dev/mem"

	depends on MMU

	tristate "AES core cipher using ARMv8 Crypto Extensions"

	depends on ARM64 && KERNEL_MODE_NEON

	select CRYPTO_ALGAPI

	select CRYPTO_AES

config CRYPTO_AES_ARM64_CE_CCM

	tristate "AES in CCM mode using ARMv8 Crypto Extensions"

	depends on ARM64 && KERNEL_MODE_NEON

	select CRYPTO_ALGAPI

	select CRYPTO_AES

	select CRYPTO_AES_ARM64_CE

	select CRYPTO_AEAD

config CRYPTO_AES_ARM64_CE_BLK

	tristate "AES in ECB/CBC/CTR/XTS modes using ARMv8 Crypto Extensions"

	depends on ARM64 && KERNEL_MODE_NEON

	select CRYPTO_BLKCIPHER

	select CRYPTO_AES

	select CRYPTO_AES_ARM64_CE

	select CRYPTO_ABLK_HELPER

config CRYPTO_AES_ARM64_NEON_BLK

#include <linux/crypto.h>

#include <linux/module.h>

#include "aes-ce-setkey.h"

static int num_rounds(struct crypto_aes_ctx *ctx)

{

	/*

	struct crypto_aes_ctx *ctx = crypto_aead_ctx(tfm);

	int ret;

	ret = crypto_aes_expand_key(ctx, in_key, key_len);

	ret = ce_aes_expandkey(ctx, in_key, key_len);

	if (!ret)

		return 0;