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Commit b6283055 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Jani Nikula
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drm/i915: Cache current cdclk frequency in dev_priv 



Rather that extracting the current cdclk freuqncy every time someone
wants to know it, cache the current value and use that. VLV/CHV already
stored a cached value there so just expand that to cover all platforms.

v2: Rebased to the latest
v3: Rebased to the latest
v4: Rebased to the latest
v5: Removed spurious call to 'intel_update_cdclk(dev)' based on
    Damien Lespiau's comment

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarMika Kahola <mika.kahola@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent ccb6662b

drivers/gpu/drm/i915/intel_display.c

+15 −9
Original line number Original line Diff line number Diff line
@@ -5747,7 +5747,7 @@ static int valleyview_get_vco(struct drm_i915_private *dev_priv) 
	return vco_freq[hpll_freq] * 1000;

	return vco_freq[hpll_freq] * 1000;

}

}





static void vlv_update_cdclk(struct drm_device *dev)

static void intel_update_cdclk(struct drm_device *dev)

{

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5755,6 +5755,12 @@ static void vlv_update_cdclk(struct drm_device *dev) 
	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",

	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",

			 dev_priv->cdclk_freq);

			 dev_priv->cdclk_freq);





	/*

	 * Program the gmbus_freq based on the cdclk frequency.

	 * BSpec erroneously claims we should aim for 4MHz, but

	 * in fact 1MHz is the correct frequency.

	 */

	if (IS_VALLEYVIEW(dev)) {

		/*

		/*

		 * Program the gmbus_freq based on the cdclk frequency.

		 * Program the gmbus_freq based on the cdclk frequency.

		 * BSpec erroneously claims we should aim for 4MHz, but

		 * BSpec erroneously claims we should aim for 4MHz, but
@@ -5762,6 +5768,7 @@ static void vlv_update_cdclk(struct drm_device *dev) 
		 */

		 */

		I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));

		I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));

	}

	}

}





/* Adjust CDclk dividers to allow high res or save power if possible */

/* Adjust CDclk dividers to allow high res or save power if possible */

static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)

static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
@@ -5826,7 +5833,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) 




	mutex_unlock(&dev_priv->sb_lock);

	mutex_unlock(&dev_priv->sb_lock);





	vlv_update_cdclk(dev);

	intel_update_cdclk(dev);

}

}





static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)

static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
@@ -5867,7 +5874,7 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) 
	}

	}

	mutex_unlock(&dev_priv->rps.hw_lock);

	mutex_unlock(&dev_priv->rps.hw_lock);





	vlv_update_cdclk(dev);

	intel_update_cdclk(dev);

}

}





static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,

static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
@@ -9479,6 +9486,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) 
	}

	}





	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

	intel_update_cdclk(dev_priv->dev);

}

}





/*

/*
@@ -13273,6 +13281,8 @@ static void intel_shared_dpll_init(struct drm_device *dev) 
{

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;





	intel_update_cdclk(dev);



	if (HAS_DDI(dev))

	if (HAS_DDI(dev))

		intel_ddi_pll_init(dev);

		intel_ddi_pll_init(dev);

	else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))

	else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
@@ -14848,13 +14858,9 @@ static void i915_disable_vga(struct drm_device *dev) 




void intel_modeset_init_hw(struct drm_device *dev)

void intel_modeset_init_hw(struct drm_device *dev)

{

{

	intel_update_cdclk(dev);

	intel_prepare_ddi(dev);

	intel_prepare_ddi(dev);



	if (IS_VALLEYVIEW(dev))

		vlv_update_cdclk(dev);



	intel_init_clock_gating(dev);

	intel_init_clock_gating(dev);



	intel_enable_gt_powersave(dev);

	intel_enable_gt_powersave(dev);

}

}