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Commit b5f00d18 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm 

Pull ARM updates from Russell King:
 "Included in this update are:

   - Patches from Gregory Clement to fix the coherent DMA cases in our
     dma-mapping code.

   - A number of CPU errata updates and fixes.

   - ARM cpuidle improvements from Jisheng Zhang.

   - Fix from Kees for the location of _etext.

   - Cleanups from Masahiro Yamada to avoid duplicated messages during
     the kernel build, and remove CONFIG_ARCH_HAS_BARRIERS.

   - Remove a udelay loop limitation, allowing for faster CPUs to
     calibrate the delay correctly.

   - Cleanup some left-overs from the SW PAN implementation.

   - Ensure that a modified address limit is not visible to exception
     handlers"

* 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (21 commits)
  ARM: 8586/1: cpuidle: make arm_cpuidle_suspend() a bit more efficient
  ARM: 8585/1: cpuidle: fix !cpuidle_ops[cpu].init case during init
  ARM: 8561/4: dma-mapping: Fix the coherent case when iommu is used
  ARM: 8561/3: dma-mapping: Don't use outer_flush_range when the L2C is coherent
  ARM: 8560/1: errata: Workaround errata A12 825619 / A17 852421
  ARM: 8559/1: errata: Workaround erratum A12 821420
  ARM: 8558/1: errata: Workaround errata A12 818325/852422 A17 852423
  ARM: save and reset the address limit when entering an exception
  ARM: 8577/1: Fix Cortex-A15 798181 errata initialization
  ARM: 8584/1: floppy: avoid gcc-6 warning
  ARM: 8583/1: mm: fix location of _etext
  ARM: 8582/1: remove unused CONFIG_ARCH_HAS_BARRIERS
  ARM: 8306/1: loop_udelay: remove bogomips value limitation
  ARM: 8581/1: add missing <asm/prom.h> to arch/arm/kernel/devtree.c
  ARM: 8576/1: avoid duplicating "Kernel: arch/arm/boot/*Image is ready"
  ARM: 8556/1: on a generic DT system: do not touch l2x0
  ARM: uaccess: remove put_user() code duplication
  ARM: 8580/1: Remove orphaned __addr_ok() definition
  ARM: get rid of horrible *(unsigned int *)(regs + 1)
  ARM: introduce svc_pt_regs structure
  ...
parents 27ae0c41 5f5a00ea

arch/arm/Kconfig

+54 −0
Original line number Diff line number Diff line
@@ -1186,6 +1186,60 @@ config ARM_ERRATA_773022 
	  loop buffer may deliver incorrect instructions. This

	  workaround disables the loop buffer to avoid the erratum.



config ARM_ERRATA_818325_852422

	bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"

	depends on CPU_V7

	help

	  This option enables the workaround for:

	  - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM

	    instruction might deadlock.  Fixed in r0p1.

	  - Cortex-A12 852422: Execution of a sequence of instructions might

	    lead to either a data corruption or a CPU deadlock.  Not fixed in

	    any Cortex-A12 cores yet.

	  This workaround for all both errata involves setting bit[12] of the

	  Feature Register. This bit disables an optimisation applied to a

	  sequence of 2 instructions that use opposing condition codes.



config ARM_ERRATA_821420

	bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"

	depends on CPU_V7

	help

	  This option enables the workaround for the 821420 Cortex-A12

	  (all revs) erratum. In very rare timing conditions, a sequence

	  of VMOV to Core registers instructions, for which the second

	  one is in the shadow of a branch or abort, can lead to a

	  deadlock when the VMOV instructions are issued out-of-order.



config ARM_ERRATA_825619

	bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"

	depends on CPU_V7

	help

	  This option enables the workaround for the 825619 Cortex-A12

	  (all revs) erratum. Within rare timing constraints, executing a

	  DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable

	  and Device/Strongly-Ordered loads and stores might cause deadlock



config ARM_ERRATA_852421

	bool "ARM errata: A17: DMB ST might fail to create order between stores"

	depends on CPU_V7

	help

	  This option enables the workaround for the 852421 Cortex-A17

	  (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,

	  execution of a DMB ST instruction might fail to properly order

	  stores from GroupA and stores from GroupB.



config ARM_ERRATA_852423

	bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"

	depends on CPU_V7

	help

	  This option enables the workaround for:

	  - Cortex-A17 852423: Execution of a sequence of instructions might

	    lead to either a data corruption or a CPU deadlock.  Not fixed in

	    any Cortex-A17 cores yet.

	  This is identical to Cortex-A12 erratum 852422.  It is a separate

	  config option from the A12 erratum due to the way errata are checked

	  for and handled.



endmenu



source "arch/arm/common/Kconfig"

arch/arm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -327,6 +327,7 @@ zImage: Image 


$(BOOT_TARGETS): vmlinux

	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@

	@$(kecho) '  Kernel: $(boot)/$@ is ready'



$(INSTALL_TARGETS):

	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@

arch/arm/boot/Makefile

+1 −5
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ ifeq ($(CONFIG_XIP_KERNEL),y) 


$(obj)/xipImage: vmlinux FORCE

	$(call if_changed,objcopy)

	@$(kecho) '  Kernel: $@ is ready (physical address: $(CONFIG_XIP_PHYS_ADDR))'

	@$(kecho) '  Physical Address of xipImage: $(CONFIG_XIP_PHYS_ADDR)'



$(obj)/Image $(obj)/zImage: FORCE

	@echo 'Kernel configured for XIP (CONFIG_XIP_KERNEL=y)'
@@ -46,14 +46,12 @@ $(obj)/xipImage: FORCE 


$(obj)/Image: vmlinux FORCE

	$(call if_changed,objcopy)

	@$(kecho) '  Kernel: $@ is ready'



$(obj)/compressed/vmlinux: $(obj)/Image FORCE

	$(Q)$(MAKE) $(build)=$(obj)/compressed $@



$(obj)/zImage:	$(obj)/compressed/vmlinux FORCE

	$(call if_changed,objcopy)

	@$(kecho) '  Kernel: $@ is ready'



endif
@@ -78,14 +76,12 @@ fi 
$(obj)/uImage:	$(obj)/zImage FORCE

	@$(check_for_multiple_loadaddr)

	$(call if_changed,uimage)

	@$(kecho) '  Image $@ is ready'



$(obj)/bootp/bootp: $(obj)/zImage initrd FORCE

	$(Q)$(MAKE) $(build)=$(obj)/bootp $@



$(obj)/bootpImage: $(obj)/bootp/bootp FORCE

	$(call if_changed,objcopy)

	@$(kecho) '  Kernel: $@ is ready'



PHONY += initrd install zinstall uinstall

initrd:

arch/arm/include/asm/assembler.h

+2 −2
Original line number Diff line number Diff line
@@ -480,13 +480,13 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) 
	.macro	uaccess_save, tmp

#ifdef CONFIG_CPU_SW_DOMAIN_PAN

	mrc	p15, 0, \tmp, c3, c0, 0

	str	\tmp, [sp, #S_FRAME_SIZE]

	str	\tmp, [sp, #SVC_DACR]

#endif

	.endm



	.macro	uaccess_restore

#ifdef CONFIG_CPU_SW_DOMAIN_PAN

	ldr	r0, [sp, #S_FRAME_SIZE]

	ldr	r0, [sp, #SVC_DACR]

	mcr	p15, 0, r0, c3, c0, 0

#endif

	.endm

arch/arm/include/asm/barrier.h

+1 −3
Original line number Diff line number Diff line
@@ -44,9 +44,7 @@ extern void arm_heavy_mb(void); 
#define __arm_heavy_mb(x...) dsb(x)

#endif



#ifdef CONFIG_ARCH_HAS_BARRIERS

#include <mach/barriers.h>

#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)

#if defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)

#define mb()		__arm_heavy_mb()

#define rmb()		dsb()

#define wmb()		__arm_heavy_mb(st)