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Commit b5e8f394 authored by Chaotian Jing's avatar Chaotian Jing Committed by Greg Kroah-Hartman
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mmc: mediatek: fix CMD_TA to 2 for MT8173 HS200/HS400 mode 



commit 8f34e5bd7024d1ffebddd82d7318b1be17be9e9a upstream.

there is a chance that always get response CRC error after HS200 tuning,
the reason is that need set CMD_TA to 2. this modification is only for
MT8173.

Signed-off-by: default avatarChaotian Jing <chaotian.jing@mediatek.com>
Tested-by: default avatarHsin-Yi Wang <hsinyi@chromium.org>
Cc: stable@vger.kernel.org
Fixes: 1ede5cb8 ("mmc: mediatek: Use data tune for CMD line tune")
Link: https://lore.kernel.org/r/20191204071958.18553-1-chaotian.jing@mediatek.com


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent f6724e07

drivers/mmc/host/mtk-sd.c

+2 −0
Original line number Diff line number Diff line
@@ -228,6 +228,7 @@ 
#define MSDC_PATCH_BIT_SPCPUSH    (0x1 << 29)	/* RW */

#define MSDC_PATCH_BIT_DECRCTMO   (0x1 << 30)	/* RW */



#define MSDC_PATCH_BIT1_CMDTA     (0x7 << 3)    /* RW */

#define MSDC_PATCH_BIT1_STOP_DLY  (0xf << 8)    /* RW */



#define MSDC_PATCH_BIT2_CFGRESP   (0x1 << 15)   /* RW */
@@ -1673,6 +1674,7 @@ static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 


	/* select EMMC50 PAD CMD tune */

	sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));

	sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);



	if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||

	    mmc->ios.timing == MMC_TIMING_UHS_SDR104)