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Commit b5d99ff9 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Fix comments about GMBUSFREQ register 



The comment about GMBUSFREQ is confused. The spec actually explains
the 4MHz thing perfectly by noting that the 4MHz divider values is
actually just bits [9:2] not [9:0], hence the divide by 1000 correct.
Replace the confused note with a quote from the spec, and eliminate
the duplicated comment that snuck in.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461689194-6079-4-git-send-email-ville.syrjala@linux.intel.com


Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
parent 1033f92e

drivers/gpu/drm/i915/intel_display.c

+5 −10
Original line number Diff line number Diff line
@@ -5329,18 +5329,13 @@ static void intel_update_cdclk(struct drm_device *dev) 
			 dev_priv->cdclk_freq);



	/*

	 * Program the gmbus_freq based on the cdclk frequency.

	 * BSpec erroneously claims we should aim for 4MHz, but

	 * in fact 1MHz is the correct frequency.

	 */

	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {

		/*

		 * Program the gmbus_freq based on the cdclk frequency.

		 * BSpec erroneously claims we should aim for 4MHz, but

		 * in fact 1MHz is the correct frequency.

	 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):

	 * Programmng [sic] note: bit[9:2] should be programmed to the number

	 * of cdclk that generates 4MHz reference clock freq which is used to

	 * generate GMBus clock. This will vary with the cdclk freq.

	 */

	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

		I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));

	}



	if (dev_priv->max_cdclk_freq == 0)

		intel_update_max_cdclk(dev);