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Commit b5b131c7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-4.6-rc1' of git://git.infradead.org/users/vkoul/slave-dma 

Pull dmaengine updates from Vinod Koul:
 "This is smallish update with minor changes to core and new driver and
  usual updates.  Nothing super exciting here..

   - We have made slave address as physical to enable driver to do the
     mapping.

   - We now expose the maxburst for slave dma as new capability so
     clients can know this and program accordingly

   - addition of device synchronize callbacks on omap and edma.

   - pl330 updates to support DMAFLUSHP for Rockchip platforms.

   - Updates and improved sg handling in Xilinx VDMA driver.

   - New hidma qualcomm dma driver, though some bits are still in
     progress"

* tag 'dmaengine-4.6-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (40 commits)
  dmaengine: IOATDMA: revise channel reset workaround on CB3.3 platforms
  dmaengine: add Qualcomm Technologies HIDMA channel driver
  dmaengine: add Qualcomm Technologies HIDMA management driver
  dmaengine: hidma: Add Device Tree binding
  dmaengine: qcom_bam_dma: move to qcom directory
  dmaengine: tegra: Move of_device_id table near to its user
  dmaengine: xilinx_vdma: Remove unnecessary variable initializations
  dmaengine: sirf: use __maybe_unused to hide pm functions
  dmaengine: rcar-dmac: clear pertinence number of channels
  dmaengine: sh: shdmac: don't open code of_device_get_match_data()
  dmaengine: tegra: don't open code of_device_get_match_data()
  dmaengine: qcom_bam_dma: Make driver work for BE
  dmaengine: sun4i: support module autoloading
  dma/mic_x100_dma: IS_ERR() vs PTR_ERR() typo
  dmaengine: xilinx_vdma: Use readl_poll_timeout instead of do while loop's
  dmaengine: xilinx_vdma: Simplify spin lock handling
  dmaengine: xilinx_vdma: Fix issues with non-parking mode
  dmaengine: xilinx_vdma: Improve SG engine handling
  dmaengine: pl330: fix to support the burst mode
  dmaengine: make slave address physical
  ...
parents c7eec380 896e041e

Documentation/ABI/testing/sysfs-platform-hidma-mgmt

0 → 100644
+97 −0
Original line number Diff line number Diff line 
What:		/sys/devices/platform/hidma-mgmt*/chanops/chan*/priority

		/sys/devices/platform/QCOM8060:*/chanops/chan*/priority

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Contains either 0 or 1 and indicates if the DMA channel is a

		low priority (0) or high priority (1) channel.



What:		/sys/devices/platform/hidma-mgmt*/chanops/chan*/weight

		/sys/devices/platform/QCOM8060:*/chanops/chan*/weight

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Contains 0..15 and indicates the weight of the channel among

		equal priority channels during round robin scheduling.



What:		/sys/devices/platform/hidma-mgmt*/chreset_timeout_cycles

		/sys/devices/platform/QCOM8060:*/chreset_timeout_cycles

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Contains the platform specific cycle value to wait after a

		reset command is issued. If the value is chosen too short,

		then the HW will issue a reset failure interrupt. The value

		is platform specific and should not be changed without

		consultance.



What:		/sys/devices/platform/hidma-mgmt*/dma_channels

		/sys/devices/platform/QCOM8060:*/dma_channels

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Contains the number of dma channels supported by one instance

		of HIDMA hardware. The value may change from chip to chip.



What:		/sys/devices/platform/hidma-mgmt*/hw_version_major

		/sys/devices/platform/QCOM8060:*/hw_version_major

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Version number major for the hardware.



What:		/sys/devices/platform/hidma-mgmt*/hw_version_minor

		/sys/devices/platform/QCOM8060:*/hw_version_minor

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Version number minor for the hardware.



What:		/sys/devices/platform/hidma-mgmt*/max_rd_xactions

		/sys/devices/platform/QCOM8060:*/max_rd_xactions

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Contains a value between 0 and 31. Maximum number of

		read transactions that can be issued back to back.

		Choosing a higher number gives better performance but

		can also cause performance reduction to other peripherals

		sharing the same bus.



What:		/sys/devices/platform/hidma-mgmt*/max_read_request

		/sys/devices/platform/QCOM8060:*/max_read_request

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Size of each read request. The value needs to be a power

		of two and can be between 128 and 1024.



What:		/sys/devices/platform/hidma-mgmt*/max_wr_xactions

		/sys/devices/platform/QCOM8060:*/max_wr_xactions

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Contains a value between 0 and 31. Maximum number of

		write transactions that can be issued back to back.

		Choosing a higher number gives better performance but

		can also cause performance reduction to other peripherals

		sharing the same bus.





What:		/sys/devices/platform/hidma-mgmt*/max_write_request

		/sys/devices/platform/QCOM8060:*/max_write_request

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Size of each write request. The value needs to be a power

		of two and can be between 128 and 1024.

Documentation/devicetree/bindings/dma/arm-pl330.txt

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ Optional properties: 
    cells in the dmas property of client device.

  - dma-channels: contains the total number of DMA channels supported by the DMAC

  - dma-requests: contains the total number of DMA requests supported by the DMAC

  - arm,pl330-broken-no-flushp: quirk for avoiding to execute DMAFLUSHP



Example:

Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt

0 → 100644
+89 −0
Original line number Diff line number Diff line 
Qualcomm Technologies HIDMA Management interface



Qualcomm Technologies HIDMA is a high speed DMA device. It only supports

memcpy and memset capabilities. It has been designed for virtualized

environments.



Each HIDMA HW instance consists of multiple DMA channels. These channels

share the same bandwidth. The bandwidth utilization can be parititioned

among channels based on the priority and weight assignments.



There are only two priority levels and 15 weigh assignments possible.



Other parameters here determine how much of the system bus this HIDMA

instance can use like maximum read/write request and and number of bytes to

read/write in a single burst.



Main node required properties:

- compatible: "qcom,hidma-mgmt-1.0";

- reg: Address range for DMA device

- dma-channels: Number of channels supported by this DMA controller.

- max-write-burst-bytes: Maximum write burst in bytes that HIDMA can

  occupy the bus for in a single transaction. A memcpy requested is

  fragmented to multiples of this amount. This parameter is used while

  writing into destination memory. Setting this value incorrectly can

  starve other peripherals in the system.

- max-read-burst-bytes: Maximum read burst in bytes that HIDMA can

  occupy the bus for in a single transaction. A memcpy request is

  fragmented to multiples of this amount. This parameter is used while

  reading the source memory. Setting this value incorrectly can starve

  other peripherals in the system.

- max-write-transactions: This value is how many times a write burst is

  applied back to back while writing to the destination before yielding

  the bus.

- max-read-transactions: This value is how many times a read burst is

  applied back to back while reading the source before yielding the bus.

- channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.

  Once a reset is applied to the HW, HW starts a timer for reset operation

  to confirm. If reset is not completed within this time, HW reports reset

  failure.



Sub-nodes:



HIDMA has one or more DMA channels that are used to move data from one

memory location to another.



When the OS is not in control of the management interface (i.e. it's a guest),

the channel nodes appear on their own, not under a management node.



Required properties:

- compatible: must contain "qcom,hidma-1.0"

- reg: Addresses for the transfer and event channel

- interrupts: Should contain the event interrupt

- desc-count: Number of asynchronous requests this channel can handle

- iommus: required a iommu node



Example:



Hypervisor OS configuration:



	hidma-mgmt@f9984000 = {

		compatible = "qcom,hidma-mgmt-1.0";

		reg = <0xf9984000 0x15000>;

		dma-channels = <6>;

		max-write-burst-bytes = <1024>;

		max-read-burst-bytes = <1024>;

		max-write-transactions = <31>;

		max-read-transactions = <31>;

		channel-reset-timeout-cycles = <0x500>;



		hidma_24: dma-controller@0x5c050000 {

			compatible = "qcom,hidma-1.0";

			reg = <0 0x5c050000 0x0 0x1000>,

			      <0 0x5c0b0000 0x0 0x1000>;

			interrupts = <0 389 0>;

			desc-count = <10>;

			iommus = <&system_mmu>;

		};

	};



Guest OS configuration:



	hidma_24: dma-controller@0x5c050000 {

		compatible = "qcom,hidma-1.0";

		reg = <0 0x5c050000 0x0 0x1000>,

		      <0 0x5c0b0000 0x0 0x1000>;

		interrupts = <0 389 0>;

		desc-count = <10>;

		iommus = <&system_mmu>;

	};

drivers/dma/Kconfig

+5 −11
Original line number Diff line number Diff line
@@ -341,12 +341,13 @@ config MV_XOR 


config MXS_DMA

	bool "MXS DMA support"

	depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q

	depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q || SOC_IMX6UL

	select STMP_DEVICE

	select DMA_ENGINE

	help

	  Support the MXS DMA engine. This engine including APBH-DMA

	  and APBX-DMA is integrated into Freescale i.MX23/28/MX6Q/MX6DL chips.

	  and APBX-DMA is integrated into Freescale

	  i.MX23/28/MX6Q/MX6DL/MX6UL chips.



config MX3_IPU

	bool "MX3x Image Processing Unit support"
@@ -408,15 +409,6 @@ config PXA_DMA 
	  16 to 32 channels for peripheral to memory or memory to memory

	  transfers.



config QCOM_BAM_DMA

	tristate "QCOM BAM DMA support"

	depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM)

	select DMA_ENGINE

	select DMA_VIRTUAL_CHANNELS

	---help---

	  Enable support for the QCOM BAM DMA controller.  This controller

	  provides DMA capabilities for a variety of on-chip devices.



config SIRF_DMA

	tristate "CSR SiRFprimaII/SiRFmarco DMA support"

	depends on ARCH_SIRF
@@ -539,6 +531,8 @@ config ZX_DMA 
# driver files

source "drivers/dma/bestcomm/Kconfig"



source "drivers/dma/qcom/Kconfig"



source "drivers/dma/dw/Kconfig"



source "drivers/dma/hsu/Kconfig"

drivers/dma/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -52,7 +52,6 @@ obj-$(CONFIG_PCH_DMA) += pch_dma.o 
obj-$(CONFIG_PL330_DMA) += pl330.o

obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/

obj-$(CONFIG_PXA_DMA) += pxa_dma.o

obj-$(CONFIG_QCOM_BAM_DMA) += qcom_bam_dma.o

obj-$(CONFIG_RENESAS_DMA) += sh/

obj-$(CONFIG_SIRF_DMA) += sirf-dma.o

obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
@@ -67,4 +66,5 @@ obj-$(CONFIG_TI_EDMA) += edma.o 
obj-$(CONFIG_XGENE_DMA) += xgene-dma.o

obj-$(CONFIG_ZX_DMA) += zx296702_dma.o



obj-y += qcom/

obj-y += xilinx/