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Commit b5964708 authored by Mark Langsdorf's avatar Mark Langsdorf Committed by Rafael J. Wysocki
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clk / highbank: Prevent glitches in non-bypass reset mode 



The highbank clock will glitch with the current code if the
clock rate is reset without relocking the PLL. Program the PLL
correctly to prevent glitches.

Signed-off-by: default avatarMark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: default avatarRob Herring <rob.herring@calxeda.com>
Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent bd603455

drivers/clk/clk-highbank.c

+2 −0
Original line number Diff line number Diff line
@@ -182,8 +182,10 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate, 
		reg |= HB_PLL_EXT_ENA;

		reg &= ~HB_PLL_EXT_BYPASS;

	} else {

		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);

		reg &= ~HB_PLL_DIVQ_MASK;

		reg |= divq << HB_PLL_DIVQ_SHIFT;

		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);

	}

	writel(reg, hbclk->reg);