Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b593c6f4 authored by Dilip Kota's avatar Dilip Kota
Browse files

ARM: dts: msm: Configure SMMU for QUP 



SMMU driver configures S1, S2 protection by parsing
the QUP device node parameters.

Change-Id: Ib3c3c3e67eddf11b1f84e63f8394950d4d18a33a
Signed-off-by: default avatarDilip Kota <dkota@codeaurora.org>
parent 52a95c85

arch/arm64/boot/dts/qcom/kona-qupv3.dtsi

+9 −21
Original line number Original line Diff line number Diff line
@@ -12,13 +12,9 @@ 
		reg = <0x9c0000 0x2000>;

		reg = <0x9c0000 0x2000>;

		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_0>;

		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_0>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;



		qcom,iommu-s1-bypass;

		iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";

		iommus = <&apps_smmu 0x5a3 0x0>;

		iommus = <&apps_smmu 0x5a3 0x0>;

			qcom,iommu-dma = "disabled";

		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;

		};

		qcom,iommu-dma = "bypass";

	};

	};





	/* Debug UART Instance for RUMI platform */

	/* Debug UART Instance for RUMI platform */
@@ -422,13 +418,9 @@ 
		reg = <0xac0000 0x2000>;

		reg = <0xac0000 0x2000>;

		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_1>;

		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_1>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;



		qcom,iommu-s1-bypass;

		iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";

		iommus = <&apps_smmu 0x43 0x0>;

		iommus = <&apps_smmu 0x43 0x0>;

			qcom,iommu-dma = "disabled";

		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;

		};

		qcom,iommu-dma = "bypass";

	};

	};





	/* Debug UART Instance for CDP/MTP platform */

	/* Debug UART Instance for CDP/MTP platform */
@@ -709,13 +701,9 @@ 
		reg = <0x8c0000 0x2000>;

		reg = <0x8c0000 0x2000>;

		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_2>;

		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_2>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;



		qcom,iommu-s1-bypass;

		iommu_qupv3_2_geni_se_cb: qcom,iommu_qupv3_2_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";

		iommus = <&apps_smmu 0x63 0x0>;

		iommus = <&apps_smmu 0x63 0x0>;

			qcom,iommu-dma = "disabled";

		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;

		};

		qcom,iommu-dma = "bypass";

	};

	};





	/*

	/*